Presentation 1996/9/27
Design parameter dependence and optimization of drain characteristics of DTMOS
S. Komatsu, R. Ikeno, H. Ito, K. Asada,
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Abstract(in English) We investigated drain current characteristics of DTMOS using 3-dimensional device simulator. We found out that as the gate and the body are connected at the side of the channel in DTMOS, the characteristics of DTMOS is varied among each position in the direction of gate width. In this paper, we analyzed the design parameter dependence of DTMOS using device simulator and suggested a method of optimizing the design parameters.
Keyword(in Japanese) (See Japanese page)
Keyword(in English) VLSI / SOI / DTMOS / Device Simulation / Threshold Voltage
Paper # VLD96-43,ED96-89,SDM96-99
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Committee VLD
Conference Date 1996/9/27(1days)
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Registration To VLSI Design Technologies (VLD)
Language JPN
Title (in Japanese) (See Japanese page)
Sub Title (in Japanese) (See Japanese page)
Title (in English) Design parameter dependence and optimization of drain characteristics of DTMOS
Sub Title (in English)
Keyword(1) VLSI
Keyword(2) SOI
Keyword(3) DTMOS
Keyword(4) Device Simulation
Keyword(5) Threshold Voltage
1st Author's Name S. Komatsu
1st Author's Affiliation Department of Electronic Engineering, University of Tokyo()
2nd Author's Name R. Ikeno
2nd Author's Affiliation Department of Electronic Engineering, University of Tokyo
3rd Author's Name H. Ito
3rd Author's Affiliation Department of Electronic Engineering, University of Tokyo
4th Author's Name K. Asada
4th Author's Affiliation Department of Electronic Engineering, University of Tokyo
Date 1996/9/27
Paper # VLD96-43,ED96-89,SDM96-99
Volume (vol) vol.96
Number (no) 259
Page pp.pp.-
#Pages 6
Date of Issue