| Presentation | 1997/3/7 A Transistor Sizing Algorithm Incorporating Layout Information Masakazu Tanaka, Masahiro Fukui, |
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| PDF Download Page | PDF download Page Link |
| Abstract(in Japanese) | (See Japanese page) |
| Abstract(in English) | We have proposed an algorithm to optimize the gate width of transistors by incorporating an accurate estimation model for the capacitance of diffusion regions in synthesized layout. Though prior works did not estimate the drain capacitance of transistors in synthesized layout, we have proposed a new approach to get an optimal set of transistor sizes by taking advantage of an accurate layout model that considers diffusion sharing and transistor folding. We formulate the layout model with a linear equation, then optimize the transistor sizes with a dynamic programming method. We have improved the sizing results by at most 10% in the critical path delay. |
| Keyword(in Japanese) | (See Japanese page) |
| Keyword(in English) | transistor / sizing / layout / diffusion sharing / delay / capacitance / optimization |
| Paper # | VLD96-100,ICD96-210 |
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| Conference Information | |
| Committee | VLD |
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| Conference Date | 1997/3/7(1days) |
| Place (in Japanese) | (See Japanese page) |
| Place (in English) | |
| Topics (in Japanese) | (See Japanese page) |
| Topics (in English) | |
| Chair | |
| Vice Chair | |
| Secretary | |
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| Paper Information | |
| Registration To | VLSI Design Technologies (VLD) |
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| Language | JPN |
| Title (in Japanese) | (See Japanese page) |
| Sub Title (in Japanese) | (See Japanese page) |
| Title (in English) | A Transistor Sizing Algorithm Incorporating Layout Information |
| Sub Title (in English) | |
| Keyword(1) | transistor |
| Keyword(2) | sizing |
| Keyword(3) | layout |
| Keyword(4) | diffusion sharing |
| Keyword(5) | delay |
| Keyword(6) | capacitance |
| Keyword(7) | optimization |
| 1st Author's Name | Masakazu Tanaka |
| 1st Author's Affiliation | Semiconductor Research Center, Matsushita Electric Industrial Co., Ltd.() |
| 2nd Author's Name | Masahiro Fukui |
| 2nd Author's Affiliation | Semiconductor Research Center, Matsushita Electric Industrial Co., Ltd. |
| Date | 1997/3/7 |
| Paper # | VLD96-100,ICD96-210 |
| Volume (vol) | vol.96 |
| Number (no) | 556 |
| Page | pp.pp.- |
| #Pages | 8 |
| Date of Issue | |