Presentation 1997/3/7
A Hardware/Software Co-simulation Environment for Micro-processor Design with HDL Simulator and OS interface
Yoshiyuki Ito, Yuichi Nakamura,
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Abstract(in English) We proposed a hardware/software co-simulation environment by RTL simulator with programing language interface. The proposed simulation environment introduces "OS interface (OSIF)" which invokes system calls in OS on the simulation platform to execute application software. The OSIF consists of data adaption facility and function correspondence management to cooperate with OS of the simulation platform. Then we show results of experiments with a R3000 compatible processor model. This environment successfully verify our processor model with SPEC benchmarks which requires various operating system services. For example, with a lisp interpreter program li, our detailed RTL description for the core part of R3000 was simulated only within 20 hours on a 100MIPS class workstation.
Keyword(in Japanese) (See Japanese page)
Keyword(in English) Hardware/Software Co-simulation / System-level Simulation / Processor Design
Paper # VLD96-97,ICD96-207
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Conference Information
Committee VLD
Conference Date 1997/3/7(1days)
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Registration To VLSI Design Technologies (VLD)
Language JPN
Title (in Japanese) (See Japanese page)
Sub Title (in Japanese) (See Japanese page)
Title (in English) A Hardware/Software Co-simulation Environment for Micro-processor Design with HDL Simulator and OS interface
Sub Title (in English)
Keyword(1) Hardware/Software Co-simulation
Keyword(2) System-level Simulation
Keyword(3) Processor Design
1st Author's Name Yoshiyuki Ito
1st Author's Affiliation C&C Research Laboratories, NEC Corporation()
2nd Author's Name Yuichi Nakamura
2nd Author's Affiliation C&C Research Laboratories, NEC Corporation
Date 1997/3/7
Paper # VLD96-97,ICD96-207
Volume (vol) vol.96
Number (no) 556
Page pp.pp.-
#Pages 7
Date of Issue