Presentation | 2002/2/26 A Study on Hierarchically Aggregated Fair Queuing (HAFQ) for High-Speed Routers by Using Network Processor Ichinoshin Maki, Hideyuki Shimonishi, Masayuki Murata, Hideo Miyahara, |
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Abstract(in Japanese) | (See Japanese page) |
Abstract(in English) | According to rapid deployment of broadband access technologies, it is becoming more important to provide fair service among connections in backbone networks. While many packet scheduling schemes at routers have been proposed to improve per-flow fairness, many of those cannot provide per-flow fair service at high-speed. We have proposed a scalable packet scheduling scheme, in which complexity can be chosen according to the router capacity. Its effectiveness has been evaluated through simulation. In general, a scheduling complexity can be evaluated if the scheduling algorithm is given. However, its quantitative complexity of hardware implementation can be fully investigated neither by simulation nor by theoretical study. Instead, we have implemented our proposed scheme on a network processor. In this paper, we discuss the implementation design issues for high-speed routers. Also, we show that the proposed scheme is excellent in both performance and scheduling complexity through our experimental measurements using the network processor. |
Keyword(in Japanese) | (See Japanese page) |
Keyword(in English) | network processor / scalability / QoS / scheduler / fairness |
Paper # | CS2001-140 |
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Committee | CS |
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Conference Date | 2002/2/26(1days) |
Place (in Japanese) | (See Japanese page) |
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Topics (in Japanese) | (See Japanese page) |
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Paper Information | |
Registration To | Communication Systems (CS) |
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Language | JPN |
Title (in Japanese) | (See Japanese page) |
Sub Title (in Japanese) | (See Japanese page) |
Title (in English) | A Study on Hierarchically Aggregated Fair Queuing (HAFQ) for High-Speed Routers by Using Network Processor |
Sub Title (in English) | |
Keyword(1) | network processor |
Keyword(2) | scalability |
Keyword(3) | QoS |
Keyword(4) | scheduler |
Keyword(5) | fairness |
1st Author's Name | Ichinoshin Maki |
1st Author's Affiliation | Graduate School of Engineering Science, Osaka University() |
2nd Author's Name | Hideyuki Shimonishi |
2nd Author's Affiliation | Networking research laboratories, NEC corporation |
3rd Author's Name | Masayuki Murata |
3rd Author's Affiliation | Graduate School of Engineering Science, Osaka University |
4th Author's Name | Hideo Miyahara |
4th Author's Affiliation | Graduate School of Engineering Science, Osaka University |
Date | 2002/2/26 |
Paper # | CS2001-140 |
Volume (vol) | vol.101 |
Number (no) | 670 |
Page | pp.pp.- |
#Pages | 7 |
Date of Issue |