| Presentation | 1993/5/17 A Very High-speed ATM Switch Architecture using A Simple Retry and Arbitration Algorithm Kouichi Genda, Naoaki Yamanaka, Yukihiro Doi, |
|---|---|
| PDF Download Page | PDF download Page Link |
| Abstract(in Japanese) | (See Japanese page) |
| Abstract(in English) | This paper proposes a very high-speed ATM switch architecture to handle Gb, s signals,named HSR switch(High-speed Statistical Retry switch).HSR switch is a matrix-shaped switch with a concentrated buffer on each input / output line.A cell is transmitted from an input buffer m times input / output line speed.A blocked cell is repeatedly transmitted from the input buffer.However,most of one cell is allowed to be successfully transmitted from each input buffer to output buffers during one cell time slot on input line. At crosspoint,cells from an upper stream crosspoint takes a preference to be transmitted.By using these simple retry and arbitration algorithm,cell loss probability at each input buffer is assured while an arbitration circuit at a crosspoint is reduced to several gates. |
| Keyword(in Japanese) | (See Japanese page) |
| Keyword(in English) | ATM / Switch / Buffer / Cell / Traffic |
| Paper # | CS93-31,OCS93-7 |
| Date of Issue |
| Conference Information | |
| Committee | CS |
|---|---|
| Conference Date | 1993/5/17(1days) |
| Place (in Japanese) | (See Japanese page) |
| Place (in English) | |
| Topics (in Japanese) | (See Japanese page) |
| Topics (in English) | |
| Chair | |
| Vice Chair | |
| Secretary | |
| Assistant | |
| Paper Information | |
| Registration To | Communication Systems (CS) |
|---|---|
| Language | JPN |
| Title (in Japanese) | (See Japanese page) |
| Sub Title (in Japanese) | (See Japanese page) |
| Title (in English) | A Very High-speed ATM Switch Architecture using A Simple Retry and Arbitration Algorithm |
| Sub Title (in English) | |
| Keyword(1) | ATM |
| Keyword(2) | Switch |
| Keyword(3) | Buffer |
| Keyword(4) | Cell |
| Keyword(5) | Traffic |
| 1st Author's Name | Kouichi Genda |
| 1st Author's Affiliation | NTT Communication Switching Laboratories() |
| 2nd Author's Name | Naoaki Yamanaka |
| 2nd Author's Affiliation | NTT Communication Switching Laboratories |
| 3rd Author's Name | Yukihiro Doi |
| 3rd Author's Affiliation | NTT Communication Switching Laboratories |
| Date | 1993/5/17 |
| Paper # | CS93-31,OCS93-7 |
| Volume (vol) | vol.93 |
| Number (no) | 25 |
| Page | pp.pp.- |
| #Pages | 7 |
| Date of Issue | |