| Presentation | 2001/1/26 A Digital Synaptic Integrated Circuit for a Large-Scale Chaotic Neuro-Computer Hirokazu OZAWA, Toshinori NAKAMURA, Yoshihiko HORIO, Kazuyuki AIHARA, |
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| PDF Download Page | PDF download Page Link |
| Abstract(in Japanese) | (See Japanese page) |
| Abstract(in English) | A digital synaptic integrated circuit for a large-scale chaotic neuro-computer, which consists of 10, 000 swiched-capacitor(SC)neurons and 100, 000, 000 synapses, is designed and fabricated.A time-division-multiplex is utilized to accommodate 10, 000 inputs in one synaptic IC.Moreover, a memory-base structure is adopted in order to realized a fast weighted-summation of 10, 000 inputs.Furthermore, a 22-bit internal date represention is used for complete liner calclation of the summation.Moreover, a data-conversion circuit that coverts the 22-bit data to an 8-bit one for the input of the SC neuron chip is integrated.Functional test circutis for each building block of the synaptic circuit are also implemented.The circuit is designed using Verilog-HDL and fabricated using an ASIC technology.The chip is tested and characterized using specially designed test benches. |
| Keyword(in Japanese) | (See Japanese page) |
| Keyword(in English) | Chaos Neuro-Computer / Neural Networks / Synaptic Circuit |
| Paper # | NLP2000-146 |
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| Conference Information | |
| Committee | NLP |
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| Conference Date | 2001/1/26(1days) |
| Place (in Japanese) | (See Japanese page) |
| Place (in English) | |
| Topics (in Japanese) | (See Japanese page) |
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| Paper Information | |
| Registration To | Nonlinear Problems (NLP) |
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| Language | JPN |
| Title (in Japanese) | (See Japanese page) |
| Sub Title (in Japanese) | (See Japanese page) |
| Title (in English) | A Digital Synaptic Integrated Circuit for a Large-Scale Chaotic Neuro-Computer |
| Sub Title (in English) | |
| Keyword(1) | Chaos Neuro-Computer |
| Keyword(2) | Neural Networks |
| Keyword(3) | Synaptic Circuit |
| 1st Author's Name | Hirokazu OZAWA |
| 1st Author's Affiliation | Dept.of Electronic Engineering, Tokyo Denki University() |
| 2nd Author's Name | Toshinori NAKAMURA |
| 2nd Author's Affiliation | Dept.of Electronic Engineering, Tokyo Denki University |
| 3rd Author's Name | Yoshihiko HORIO |
| 3rd Author's Affiliation | Dept.of Electronic Engineering, Tokyo Denki University |
| 4th Author's Name | Kazuyuki AIHARA |
| 4th Author's Affiliation | University of Tokyo, CREST, JST |
| Date | 2001/1/26 |
| Paper # | NLP2000-146 |
| Volume (vol) | vol.100 |
| Number (no) | 609 |
| Page | pp.pp.- |
| #Pages | 6 |
| Date of Issue | |