| Presentation | 2000/7/13 Application to Square Rooting Circuit for High-Speed Redundant Binary Adder-Subtractor Representing Each Digit by Hybrid 2 Bits / 3 Bits Mitsuki Hinosugi, Yoshitaka Tsunekawa, Mamoru Miura, |
|---|---|
| PDF Download Page | PDF download Page Link |
| Abstract(in Japanese) | (See Japanese page) |
| Abstract(in English) | We have proposed the very high-speed redundant binary adder-subtractor using a hybrid representation method, which attempts to represent each digit by hybrid 2 bits / 3 bits. In this report, the adder-subtractor is applied to the square rooting circuit. Several structure methods of aquare rooting circuit have been proposed, and we consider the structure method for the purpose of high-speed. Finally, by using PARTHENON, a CAD (Computer Aided Design) system for VLSI, this square rooting circuit is designed and evaluated, based on 5 volt, 0.6 μm CMOS process technology. As a result, we show that the speed of the proposed square rooting circuit can be about 1.6 times as compared with the conventional square rooting circuit. |
| Keyword(in Japanese) | (See Japanese page) |
| Keyword(in English) | square rooting circuit / redundant binary representation / high-speed / adder-subtractor / VLSI evaluation |
| Paper # | CAS2000-53,NLP2000-61 |
| Date of Issue |
| Conference Information | |
| Committee | NLP |
|---|---|
| Conference Date | 2000/7/13(1days) |
| Place (in Japanese) | (See Japanese page) |
| Place (in English) | |
| Topics (in Japanese) | (See Japanese page) |
| Topics (in English) | |
| Chair | |
| Vice Chair | |
| Secretary | |
| Assistant | |
| Paper Information | |
| Registration To | Nonlinear Problems (NLP) |
|---|---|
| Language | JPN |
| Title (in Japanese) | (See Japanese page) |
| Sub Title (in Japanese) | (See Japanese page) |
| Title (in English) | Application to Square Rooting Circuit for High-Speed Redundant Binary Adder-Subtractor Representing Each Digit by Hybrid 2 Bits / 3 Bits |
| Sub Title (in English) | |
| Keyword(1) | square rooting circuit |
| Keyword(2) | redundant binary representation |
| Keyword(3) | high-speed |
| Keyword(4) | adder-subtractor |
| Keyword(5) | VLSI evaluation |
| 1st Author's Name | Mitsuki Hinosugi |
| 1st Author's Affiliation | Faculty of Engineering, Iwate University() |
| 2nd Author's Name | Yoshitaka Tsunekawa |
| 2nd Author's Affiliation | Faculty of Engineering, Iwate University |
| 3rd Author's Name | Mamoru Miura |
| 3rd Author's Affiliation | Faculty of Engineering, Iwate University |
| Date | 2000/7/13 |
| Paper # | CAS2000-53,NLP2000-61 |
| Volume (vol) | vol.100 |
| Number (no) | 205 |
| Page | pp.pp.- |
| #Pages | 8 |
| Date of Issue | |