Presentation | 1998/5/15 A Study of Ternary Logic Circuit by using Logic Oriented Neural Networks Masahiro Sakamoto, Junichi Yamada, Mititada Morisue, |
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Abstract(in Japanese) | (See Japanese page) |
Abstract(in English) | This paper describes a novel design method of ternary logic circuit by using Logic Oriented(LOGO) neural network. It allows to design signed ternary logic circuit in a simple way. First, we describe a implementation method of LOGO neural networks with the current-mode MOSFET circuit. Then we design a ternary logical sum and logical product gate, a half adder, a set-reset flip-flop and delay flip flop by using LOGO neural networks. In order to verify the function of the proposed circuits, simulations have been made by SPICE program. |
Keyword(in Japanese) | (See Japanese page) |
Keyword(in English) | logic oriented neural network / tenary logic circuit / MOSFET |
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Committee | NLP |
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Conference Date | 1998/5/15(1days) |
Place (in Japanese) | (See Japanese page) |
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Topics (in Japanese) | (See Japanese page) |
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Registration To | Nonlinear Problems (NLP) |
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Language | JPN |
Title (in Japanese) | (See Japanese page) |
Sub Title (in Japanese) | (See Japanese page) |
Title (in English) | A Study of Ternary Logic Circuit by using Logic Oriented Neural Networks |
Sub Title (in English) | |
Keyword(1) | logic oriented neural network |
Keyword(2) | tenary logic circuit |
Keyword(3) | MOSFET |
1st Author's Name | Masahiro Sakamoto |
1st Author's Affiliation | Faculty of Information sciences, Hiroshima City University() |
2nd Author's Name | Junichi Yamada |
2nd Author's Affiliation | Faculty of Information sciences, Hiroshima City University |
3rd Author's Name | Mititada Morisue |
3rd Author's Affiliation | Faculty of Information sciences, Hiroshima City University |
Date | 1998/5/15 |
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Volume (vol) | vol.98 |
Number (no) | 45 |
Page | pp.pp.- |
#Pages | 8 |
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