| Presentation | 1997/2/21 A study of flexible hardware design method for ATM node systems Tsuneo Matsumura, Naoaki Yamanaka, Ryoichi Yamaguchi, Keiji Ishikawa, |
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| PDF Download Page | PDF download Page Link |
| Abstract(in Japanese) | (See Japanese page) |
| Abstract(in English) | This paper describes a real-time emulation method based on the use of commercial FPGAs high-speed interconnect switch devices and software tools to emulate large scale high-speed ATM node system without the need for conventional specific wiring structures between FPGAs and timing control circuit insertion. This method is applied to line interface units (LUs) that have 20 MHz operation ; we employ the LU board and emulation boards, both of which have hierarchical structures with sub-boards. The proposed LU structure has the advantage of utilizing a common LU board for rapid prototyping as well as developing cost effective, practical high-performance ATM node systems. The results of multiple FPGA partitioning on the emulation board suggest that the proposed method will yield economic systems that are also practical. |
| Keyword(in Japanese) | (See Japanese page) |
| Keyword(in English) | ATM / Line Interface Unit (LU) / Hardware Design / Emulation / FPGA (Field Programmable Gate Array) / Prototype |
| Paper # | SSE96-165,OCS96-103 |
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| Conference Information | |
| Committee | OCS |
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| Conference Date | 1997/2/21(1days) |
| Place (in Japanese) | (See Japanese page) |
| Place (in English) | |
| Topics (in Japanese) | (See Japanese page) |
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| Paper Information | |
| Registration To | Optical Communication Systems (OCS) |
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| Language | JPN |
| Title (in Japanese) | (See Japanese page) |
| Sub Title (in Japanese) | (See Japanese page) |
| Title (in English) | A study of flexible hardware design method for ATM node systems |
| Sub Title (in English) | |
| Keyword(1) | ATM |
| Keyword(2) | Line Interface Unit (LU) |
| Keyword(3) | Hardware Design |
| Keyword(4) | Emulation |
| Keyword(5) | FPGA (Field Programmable Gate Array) |
| Keyword(6) | Prototype |
| 1st Author's Name | Tsuneo Matsumura |
| 1st Author's Affiliation | NTT Network Service Systems Laboratories() |
| 2nd Author's Name | Naoaki Yamanaka |
| 2nd Author's Affiliation | NTT Network Service Systems Laboratories |
| 3rd Author's Name | Ryoichi Yamaguchi |
| 3rd Author's Affiliation | NTT Network Service Systems Laboratories |
| 4th Author's Name | Keiji Ishikawa |
| 4th Author's Affiliation | NTT Network Service Systems Laboratories |
| Date | 1997/2/21 |
| Paper # | SSE96-165,OCS96-103 |
| Volume (vol) | vol.96 |
| Number (no) | 538 |
| Page | pp.pp.- |
| #Pages | 6 |
| Date of Issue | |