Presentation 1997/2/21
Input and Output Queueing Packet Switch with Backpressure Mode in Discarding Policy
Takeshi Kanazawa, Toshiki Endo, Masaki Umayabashi, Iwao Sasase,
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Abstract(in English) Input and output queueing packet switch model with backpressure mode in discarding policy is proposed In the proposed model, delay sensitive packets gain an advantage over loss sensitive packets at input and output ports and backpressure mode is applied for loss sensitive packets. We evaluate the average system delay and the packet loss probability of each class by theoretical calculation and computer simulation. As the results, we show that this model is useful to decrease the average system delay of delay sensitive packets and the packer loss probability of loss Sensitive packets.
Keyword(in Japanese) (See Japanese page)
Keyword(in English) input and output queueing packet switch / priority classes / discarding policy / backpressure mode / average system delay / packet loss probability
Paper # SSE96-162,OCS96-100
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Committee OCS
Conference Date 1997/2/21(1days)
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Registration To Optical Communication Systems (OCS)
Language JPN
Title (in Japanese) (See Japanese page)
Sub Title (in Japanese) (See Japanese page)
Title (in English) Input and Output Queueing Packet Switch with Backpressure Mode in Discarding Policy
Sub Title (in English)
Keyword(1) input and output queueing packet switch
Keyword(2) priority classes
Keyword(3) discarding policy
Keyword(4) backpressure mode
Keyword(5) average system delay
Keyword(6) packet loss probability
1st Author's Name Takeshi Kanazawa
1st Author's Affiliation Department of Electrical Engineering, Faculty of Science and Technology, Keio University()
2nd Author's Name Toshiki Endo
2nd Author's Affiliation Department of Electrical Engineering, Faculty of Science and Technology, Keio University
3rd Author's Name Masaki Umayabashi
3rd Author's Affiliation Department of Electrical Engineering, Faculty of Science and Technology, Keio University
4th Author's Name Iwao Sasase
4th Author's Affiliation Department of Electrical Engineering, Faculty of Science and Technology, Keio University
Date 1997/2/21
Paper # SSE96-162,OCS96-100
Volume (vol) vol.96
Number (no) 538
Page pp.pp.-
#Pages 6
Date of Issue