| Presentation | 2001/10/19 High Performance DSP Architecture with Quadruple MACs Daiji ISHII, Masao IKEKAWA, Ichiro KURODA, |
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| PDF Download Page | PDF download Page Link |
| Abstract(in Japanese) | (See Japanese page) |
| Abstract(in English) | In this paper, a novel programmable digital signal processor (DSP) architecture with four multipliers suited for wireless applications is proposed, and software implementation methods of basic applications such as FIR filtering and adaptive filtering are presented to take advantage of the DSP architecture. |
| Keyword(in Japanese) | (See Japanese page) |
| Keyword(in English) | DSP / Complex multiply / 32-bit data bus / FIR filter / LMS adaptive filter |
| Paper # | DSP2001-124,ICD2001-129,IE2001-108 |
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| Conference Information | |
| Committee | DSP |
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| Conference Date | 2001/10/19(1days) |
| Place (in Japanese) | (See Japanese page) |
| Place (in English) | |
| Topics (in Japanese) | (See Japanese page) |
| Topics (in English) | |
| Chair | |
| Vice Chair | |
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| Assistant | |
| Paper Information | |
| Registration To | Digital Signal Processing (DSP) |
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| Language | JPN |
| Title (in Japanese) | (See Japanese page) |
| Sub Title (in Japanese) | (See Japanese page) |
| Title (in English) | High Performance DSP Architecture with Quadruple MACs |
| Sub Title (in English) | |
| Keyword(1) | DSP |
| Keyword(2) | Complex multiply |
| Keyword(3) | 32-bit data bus |
| Keyword(4) | FIR filter |
| Keyword(5) | LMS adaptive filter |
| 1st Author's Name | Daiji ISHII |
| 1st Author's Affiliation | Multimedia Research Laboratories, NEC Corporation() |
| 2nd Author's Name | Masao IKEKAWA |
| 2nd Author's Affiliation | Multimedia Research Laboratories, NEC Corporation |
| 3rd Author's Name | Ichiro KURODA |
| 3rd Author's Affiliation | Multimedia Research Laboratories, NEC Corporation |
| Date | 2001/10/19 |
| Paper # | DSP2001-124,ICD2001-129,IE2001-108 |
| Volume (vol) | vol.101 |
| Number (no) | 384 |
| Page | pp.pp.- |
| #Pages | 8 |
| Date of Issue | |