| Presentation | 2001/10/19 An Area-Effective Superscalar Datapath Architecture Suitable for Embedded Multimedia Processors Toshiaki INOUE, Takashi MANABE, Sunao TORII, Satoshi MATSUSHITA, Masato EDAHIRO, Naoki NISHI, Masakazu YAMASHINA, |
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| PDF Download Page | PDF download Page Link |
| Abstract(in Japanese) | (See Japanese page) |
| Abstract(in English) | We have developed a superscalar datapath unit with 34 SIMD instructions suitable for embedded multimedia processors. The unit's design is both functionally asymmetrical and integer-SIMD unified, and the resulting savings in area are 27%-48% as compared to other, functionally equivalent mid-level microprocessor designs, with performance that is, at most, only 7.2% lower. Further, in 2-D IDCT processing, the unit outperforms embedded microprocessor designs without SIMD functions by 49%-118%. These area-effective techniques are useful for embedded microprocessors and scalable systems that employ highly parallel superscalar and on-chip parallel architectures. The integer-media unit has been implemented in an evaluation chip fabricated with 0.15-um CMOS technology. |
| Keyword(in Japanese) | (See Japanese page) |
| Keyword(in English) | multiplier / datapath / superscalar / embedded processor / parallel processor / SIMD |
| Paper # | DSP2001-1121,ICD2001-126,IE2001-105 |
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| Conference Information | |
| Committee | DSP |
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| Conference Date | 2001/10/19(1days) |
| Place (in Japanese) | (See Japanese page) |
| Place (in English) | |
| Topics (in Japanese) | (See Japanese page) |
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| Chair | |
| Vice Chair | |
| Secretary | |
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| Paper Information | |
| Registration To | Digital Signal Processing (DSP) |
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| Language | JPN |
| Title (in Japanese) | (See Japanese page) |
| Sub Title (in Japanese) | (See Japanese page) |
| Title (in English) | An Area-Effective Superscalar Datapath Architecture Suitable for Embedded Multimedia Processors |
| Sub Title (in English) | |
| Keyword(1) | multiplier |
| Keyword(2) | datapath |
| Keyword(3) | superscalar |
| Keyword(4) | embedded processor |
| Keyword(5) | parallel processor |
| Keyword(6) | SIMD |
| 1st Author's Name | Toshiaki INOUE |
| 1st Author's Affiliation | NEC Corporation() |
| 2nd Author's Name | Takashi MANABE |
| 2nd Author's Affiliation | NEC Corporation |
| 3rd Author's Name | Sunao TORII |
| 3rd Author's Affiliation | NEC Corporation |
| 4th Author's Name | Satoshi MATSUSHITA |
| 4th Author's Affiliation | NEC Corporation |
| 5th Author's Name | Masato EDAHIRO |
| 5th Author's Affiliation | NEC Corporation |
| 6th Author's Name | Naoki NISHI |
| 6th Author's Affiliation | NEC Corporation |
| 7th Author's Name | Masakazu YAMASHINA |
| 7th Author's Affiliation | NEC Corporation |
| Date | 2001/10/19 |
| Paper # | DSP2001-1121,ICD2001-126,IE2001-105 |
| Volume (vol) | vol.101 |
| Number (no) | 384 |
| Page | pp.pp.- |
| #Pages | 8 |
| Date of Issue | |