| Presentation | 2001/10/19 A Technique to Suppress Performance Degradation on VT-CMOS Data Cache using Address Prediction Ryo FUJIOKA, Kiyokazu KATAYAMA, Ryotaro KOBAYASHI, Hideki ANDO, Toshio SHIMADA, |
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| PDF Download Page | PDF download Page Link |
| Abstract(in Japanese) | (See Japanese page) |
| Abstract(in English) | As the threshold voltage in CMOS circuits goes low, the leakage current, which is ignored so far, increases. This paper proposes a technique that suppresses processor performance degradation when a power-control scheme, called Dynamic Leakage Cut-off (DLC), is adopted to VT-CMOS cache. The DLC scheme causes a long delay to activate circuits in a selected line, leading Performance degradation. Our schemes predict a reference line with address prediction and changes the threshold voltage to the low level in advance. As a result, the delay of changing the threshold voltage is hidden and performance degradation is suppressed. Our results show that our mechanism can suppress performance loss to 17.2% and 3.1% on average for SPECint95 benchmark and SPECfp95 benchmark respectively, while the conventional DLC cache degrades performance by 23.2% and 9.7% respectively. The results also show that our mechanism slightly increases the leakage power over the DLC cache, but can still reduce the power to approximately 1% of that of the usual non-DLC cache. |
| Keyword(in Japanese) | (See Japanese page) |
| Keyword(in English) | leakage current / L1 data cache / VT-CMOS / address prediction |
| Paper # | DSP2001-120,ICD2001-125,IE2001-104 |
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| Conference Information | |
| Committee | DSP |
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| Conference Date | 2001/10/19(1days) |
| Place (in Japanese) | (See Japanese page) |
| Place (in English) | |
| Topics (in Japanese) | (See Japanese page) |
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| Paper Information | |
| Registration To | Digital Signal Processing (DSP) |
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| Language | JPN |
| Title (in Japanese) | (See Japanese page) |
| Sub Title (in Japanese) | (See Japanese page) |
| Title (in English) | A Technique to Suppress Performance Degradation on VT-CMOS Data Cache using Address Prediction |
| Sub Title (in English) | |
| Keyword(1) | leakage current |
| Keyword(2) | L1 data cache |
| Keyword(3) | VT-CMOS |
| Keyword(4) | address prediction |
| 1st Author's Name | Ryo FUJIOKA |
| 1st Author's Affiliation | Department of Information Electronics, Graduate School of Engineering, Nagoya University() |
| 2nd Author's Name | Kiyokazu KATAYAMA |
| 2nd Author's Affiliation | Department of Information Electronics, Graduate School of Engineering, Nagoya University |
| 3rd Author's Name | Ryotaro KOBAYASHI |
| 3rd Author's Affiliation | Department of Information Electronics, Graduate School of Engineering, Nagoya University |
| 4th Author's Name | Hideki ANDO |
| 4th Author's Affiliation | Department of Information Electronics, Graduate School of Engineering, Nagoya University |
| 5th Author's Name | Toshio SHIMADA |
| 5th Author's Affiliation | Department of Information Electronics, Graduate School of Engineering, Nagoya University |
| Date | 2001/10/19 |
| Paper # | DSP2001-120,ICD2001-125,IE2001-104 |
| Volume (vol) | vol.101 |
| Number (no) | 384 |
| Page | pp.pp.- |
| #Pages | 8 |
| Date of Issue | |