| Presentation | 2001/10/19 A Low-Power, High-Speed, Small, 0.13-μm CMOS Square Root Circuit Chihiro Oda, Hiroaki Shikano, Tomochika Harada, Tadayoshi Enomoto, |
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| PDF Download Page | PDF download Page Link |
| Abstract(in Japanese) | (See Japanese page) |
| Abstract(in English) | Compact, high-speed, low-power circuit techniques have been developed for square root circuits. MOSFETs with low-threshold voltage were used for critical paths and MOSFETs with high-threshold voltage were used in the non-critical path circuits, so that not only high-speed performance can be guaranteed, but also power dissipations in both an active-mode and a stand-by-mode can be reduced. A square root algorithm has been proposed to reduce both circuit volume and critical-path lengths. Square root circuits wers designed using 0.13-μm CMOS technology to examine the effectiveness of new techniques in power reduction and speed improvement. SPICE simulation results showed that the maximum operating clock frequency of the 8-bit square root circuit was 620 MHz that was 1.67 times faster than that of the conventional 8-bit square root circuit. The active power of the 8-bit square root circuit at 200 MHz was 404.9 μW, a reduction to 60.9% of that of the conventional 8-bit square root circuit. The stand-by power of the 8-bit square root circuit was 107.9 nW, a reduction to 34.1% of that of the equivalent 8-bit circuit. |
| Keyword(in Japanese) | (See Japanese page) |
| Keyword(in English) | CMOS / power dissipation / square root circuits / divider currents / full adder |
| Paper # | DSP2001-119,ICD2001-124,IE2001-103 |
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| Conference Information | |
| Committee | DSP |
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| Conference Date | 2001/10/19(1days) |
| Place (in Japanese) | (See Japanese page) |
| Place (in English) | |
| Topics (in Japanese) | (See Japanese page) |
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| Paper Information | |
| Registration To | Digital Signal Processing (DSP) |
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| Language | JPN |
| Title (in Japanese) | (See Japanese page) |
| Sub Title (in Japanese) | (See Japanese page) |
| Title (in English) | A Low-Power, High-Speed, Small, 0.13-μm CMOS Square Root Circuit |
| Sub Title (in English) | |
| Keyword(1) | CMOS |
| Keyword(2) | power dissipation |
| Keyword(3) | square root circuits |
| Keyword(4) | divider currents |
| Keyword(5) | full adder |
| 1st Author's Name | Chihiro Oda |
| 1st Author's Affiliation | Graduate School of Science and Engineering, Chuo University() |
| 2nd Author's Name | Hiroaki Shikano |
| 2nd Author's Affiliation | Graduate School of Science and Engineering, Chuo University |
| 3rd Author's Name | Tomochika Harada |
| 3rd Author's Affiliation | Graduate School of Science and Engineering, Chuo University |
| 4th Author's Name | Tadayoshi Enomoto |
| 4th Author's Affiliation | Graduate School of Science and Engineering, Chuo University |
| Date | 2001/10/19 |
| Paper # | DSP2001-119,ICD2001-124,IE2001-103 |
| Volume (vol) | vol.101 |
| Number (no) | 384 |
| Page | pp.pp.- |
| #Pages | 8 |
| Date of Issue | |