Presentation 2001/10/19
QVGA/CIF Resolution MPEG-4 Video Codec Based on A Low Power DSP
Atsushi HATABU, Takashi MIYAZAKI, Ichiro KURODA,
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Abstract(in Japanese) (See Japanese page)
Abstract(in English) This paper describes a QVGA/CIF resolution MPEG-4 video codec based on a low-power and general-purpose DSP (uPD77210, 160MHz, 80mW). The codec software on the DSP employs many acceleration methods. The computational cost of motion estimation is reduced by optimizing execution intervals of decision to discontinue block-matching calculation in SSDA algorithm. A software DMA queue restrains the performance degradation caused by data transfer between the DSP and its external memory. Consequently, the codec operates QVGA, 15fps or CIF, 12fps encoding and decoding, and CIF, 15fps encoding in real time.
Keyword(in Japanese) (See Japanese page)
Keyword(in English) MPEG-4 / video compression / low power consumption / DSP / QVGA / CIF / motion estimation / SSDA / DMA
Paper # DSP2001-115,ICD2001-120,IE2001-99
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Conference Information
Committee DSP
Conference Date 2001/10/19(1days)
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Paper Information
Registration To Digital Signal Processing (DSP)
Language JPN
Title (in Japanese) (See Japanese page)
Sub Title (in Japanese) (See Japanese page)
Title (in English) QVGA/CIF Resolution MPEG-4 Video Codec Based on A Low Power DSP
Sub Title (in English)
Keyword(1) MPEG-4
Keyword(2) video compression
Keyword(3) low power consumption
Keyword(4) DSP
Keyword(5) QVGA
Keyword(6) CIF
Keyword(7) motion estimation
Keyword(8) SSDA
Keyword(9) DMA
1st Author's Name Atsushi HATABU
1st Author's Affiliation Multimedia Research Laboratories, NEC Corporation()
2nd Author's Name Takashi MIYAZAKI
2nd Author's Affiliation Multimedia Research Laboratories, NEC Corporation
3rd Author's Name Ichiro KURODA
3rd Author's Affiliation Multimedia Research Laboratories, NEC Corporation
Date 2001/10/19
Paper # DSP2001-115,ICD2001-120,IE2001-99
Volume (vol) vol.101
Number (no) 384
Page pp.pp.-
#Pages 7
Date of Issue