Presentation 2001/10/19
Improvement of the AES cryptography circuit using FPGA
Hidenori SEIKE, Takakazu KUROKAWA,
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Abstract(in English) NIST decided a cryptography algorithm named Rijndael for AES (Advanced Encryption Standard) in October 2000. We are realizing an AES hardware system using FPGA. The target device is Virtex XCV300PQ240-4 from Xilinx Corp. Our previous research discussed the circuit design of the basic elements for AES such as S-box, Mix columns, and so on. Using these design data, we are trying to implement the encryption circuit as well as the decryption circuit into a single FPGA chip. For this implementation, we need to redesign the basic elements for AES to reduce their hardware size and also to improve their computational speed. This paper shows our latest implementation results.
Keyword(in Japanese) (See Japanese page)
Keyword(in English) AES / Rijndael / FPGA / Virtex / hardware / implementation
Paper # DSP2001-112,ICD2001-117,IE2001-96
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Conference Information
Committee DSP
Conference Date 2001/10/19(1days)
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Registration To Digital Signal Processing (DSP)
Language JPN
Title (in Japanese) (See Japanese page)
Sub Title (in Japanese) (See Japanese page)
Title (in English) Improvement of the AES cryptography circuit using FPGA
Sub Title (in English)
Keyword(1) AES
Keyword(2) Rijndael
Keyword(3) FPGA
Keyword(4) Virtex
Keyword(5) hardware
Keyword(6) implementation
1st Author's Name Hidenori SEIKE
1st Author's Affiliation Department of Computer Science, National Defense Academy()
2nd Author's Name Takakazu KUROKAWA
2nd Author's Affiliation Department of Computer Science, National Defense Academy
Date 2001/10/19
Paper # DSP2001-112,ICD2001-117,IE2001-96
Volume (vol) vol.101
Number (no) 384
Page pp.pp.-
#Pages 7
Date of Issue