Presentation	2001/10/19 Desgin of a VLSI Image Processor Based on a Periodical Memory Allocation Masanori HARIYAMA, Michitaka KAMEYAMA,
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Abstract(in English)	Parallel memory access with the minimum hardware cost plays an essential role for design of VLSI processors for highly parallel image processing. For the purpose, it is desired to find a memory allocation with a minimum memory capacity and the minimum number of memory modules. Exhaustive search is impractical since its execution time grows rapidly with an image size. This paper presents an efficient search method based on a periodical allocation where an allocation for a total image is obtained by repeating an allocation for a sub-image periodically.
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Keyword(in English)	logic-in-memory architecture / high-level synthesis / window operation / ASIC
Paper #	DSP2001-111,ICD2001-116,IE2001-95
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Conference Information
Committee	DSP
Conference Date	2001/10/19(1days)
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Paper Information
Registration To	Digital Signal Processing (DSP)
Language	JPN
Title (in Japanese)	(See Japanese page)
Sub Title (in Japanese)	(See Japanese page)
Title (in English)	Desgin of a VLSI Image Processor Based on a Periodical Memory Allocation
Sub Title (in English)
Keyword(1)	logic-in-memory architecture
Keyword(2)	high-level synthesis
Keyword(3)	window operation
Keyword(4)	ASIC
1st Author's Name	Masanori HARIYAMA
1st Author's Affiliation	Graduate School of Information Sciences, Tohoku University()
2nd Author's Name	Michitaka KAMEYAMA
2nd Author's Affiliation	Graduate School of Information Sciences, Tohoku University
Date	2001/10/19
Paper #	DSP2001-111,ICD2001-116,IE2001-95
Volume (vol)	vol.101
Number (no)	384
Page	pp.pp.-
#Pages	6
Date of Issue