| Presentation | 2001/10/19 Performance Evaluation of Wave-Pipelines and Conventional Pipelines Masa-aki Fukase, Ryusuke Egawa, Tomoaki Sato, Syunsuke Itoh, Tadao Nakamura, |
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| PDF Download Page | PDF download Page Link |
| Abstract(in Japanese) | (See Japanese page) |
| Abstract(in English) | Wave-pipelines are being studied for improving processors because they are expected to show high frequency, small space, and low power due to a completely different synchronization from currently dominant pipelines. While the designing and tuning of conventional pipelines are still extensively investigated, the development of wave-pipelines has really started in recent years and thus their evaluation is not always steady. In this respect, we evaluate various circuits wave-pipelined at the level of logic synthesis, prototyping by a FPGA, and implementing in a standard cell chip. They are compared with conventional pipelines regarding clocks, gate counts, and CPU times. In case of a scalar processing unit by a 0.5-μm CMOS technology, its wave-pipelined circuit uses 10% less gates. Then, a processor embedded with the wave-pipelined scalar processing unit works at a 3.3 to 5 times higher clock frequency than UltraSPARC and Alpha21164 produced by technologies of the same generation. The processor reduces the CPU time of standard test programs by 31 to 66% than those conventional processors. Thus, the superiority of wave-pipelines is made clear in every aspect. |
| Keyword(in Japanese) | (See Japanese page) |
| Keyword(in English) | Wave-pipeline / Processor / Multifunctional unit / Standard cell / FPGA / Simulation |
| Paper # | DSP2001-110,ICD2001-115,IE2001-94 |
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| Conference Information | |
| Committee | DSP |
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| Conference Date | 2001/10/19(1days) |
| Place (in Japanese) | (See Japanese page) |
| Place (in English) | |
| Topics (in Japanese) | (See Japanese page) |
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| Paper Information | |
| Registration To | Digital Signal Processing (DSP) |
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| Language | JPN |
| Title (in Japanese) | (See Japanese page) |
| Sub Title (in Japanese) | (See Japanese page) |
| Title (in English) | Performance Evaluation of Wave-Pipelines and Conventional Pipelines |
| Sub Title (in English) | |
| Keyword(1) | Wave-pipeline |
| Keyword(2) | Processor |
| Keyword(3) | Multifunctional unit |
| Keyword(4) | Standard cell |
| Keyword(5) | FPGA |
| Keyword(6) | Simulation |
| 1st Author's Name | Masa-aki Fukase |
| 1st Author's Affiliation | Faculty of Science and Technology, Hirosaki University() |
| 2nd Author's Name | Ryusuke Egawa |
| 2nd Author's Affiliation | Graduate School of Information Sciences, Tohoku University |
| 3rd Author's Name | Tomoaki Sato |
| 3rd Author's Affiliation | Faculty of Social Information, Sapporo Gakuin University |
| 4th Author's Name | Syunsuke Itoh |
| 4th Author's Affiliation | JR EAST JAPAN |
| 5th Author's Name | Tadao Nakamura |
| 5th Author's Affiliation | Graduate School of Information Sciences, Tohoku University |
| Date | 2001/10/19 |
| Paper # | DSP2001-110,ICD2001-115,IE2001-94 |
| Volume (vol) | vol.101 |
| Number (no) | 384 |
| Page | pp.pp.- |
| #Pages | 8 |
| Date of Issue | |