| Presentation | 2000/6/16 Optimization Methods for the positions of Decoupling Capacitors on Printed Circuit Board using Krylov-subspace Technique Atsushi KAMO, Takayuki WATANABE, Hideki ASAI, |
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| PDF Download Page | PDF download Page Link |
| Abstract(in Japanese) | (See Japanese page) |
| Abstract(in English) | This report investigates the optimization method for the position of the decoupling capacitor on the printed circuit board(PCB). This method minimizes the impedance characteristics at the power supply in frequency domain, searching the optimal position of decoupling capacitor. In this method, the PCB is modeled as the PEEC model to handle the three-dimensional structures. Furthermore Krylov-subspace technique is used in order to obtain efficiently the impedance characteristics in frequency domain. |
| Keyword(in Japanese) | (See Japanese page) |
| Keyword(in English) | Krylov-subspace technique / PEEC(partial element equivalent circuit) / network reduction / decoupling capacitor / PCB(printed circuit board) |
| Paper # | CAS2000-36,VLD2000-45,DSP2000-57 |
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| Conference Information | |
| Committee | DSP |
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| Conference Date | 2000/6/16(1days) |
| Place (in Japanese) | (See Japanese page) |
| Place (in English) | |
| Topics (in Japanese) | (See Japanese page) |
| Topics (in English) | |
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| Secretary | |
| Assistant | |
| Paper Information | |
| Registration To | Digital Signal Processing (DSP) |
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| Language | JPN |
| Title (in Japanese) | (See Japanese page) |
| Sub Title (in Japanese) | (See Japanese page) |
| Title (in English) | Optimization Methods for the positions of Decoupling Capacitors on Printed Circuit Board using Krylov-subspace Technique |
| Sub Title (in English) | |
| Keyword(1) | Krylov-subspace technique |
| Keyword(2) | PEEC(partial element equivalent circuit) |
| Keyword(3) | network reduction |
| Keyword(4) | decoupling capacitor |
| Keyword(5) | PCB(printed circuit board) |
| 1st Author's Name | Atsushi KAMO |
| 1st Author's Affiliation | Department of Systems Engineering, Faculty of Engineering, Shizuoka University() |
| 2nd Author's Name | Takayuki WATANABE |
| 2nd Author's Affiliation | School of Administration and Informatics, University of Shizuoka |
| 3rd Author's Name | Hideki ASAI |
| 3rd Author's Affiliation | Department of Systems Engineering, Faculty of Engineering, Shizuoka University |
| Date | 2000/6/16 |
| Paper # | CAS2000-36,VLD2000-45,DSP2000-57 |
| Volume (vol) | vol.100 |
| Number (no) | 123 |
| Page | pp.pp.- |
| #Pages | 6 |
| Date of Issue | |