| Presentation | 2000/6/15 CAS2000-15 / VLD2000-24 / DSP2000-36 A General and Fast Floorplanning by Reduct-Seq Representation Keishi SAKANUSHI, Kentarou MIDORIKAWA, Yoji KAJITANI, |
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| PDF Download Page | PDF download Page Link |
| Abstract(in Japanese) | (See Japanese page) |
| Abstract(in English) | A fundamental issue in floorplan design is in how to represent a candidate solution. After discussing the difference between floorplanning and packing, this paper proposes a new data structure Reduct-Seq for floorplan. A floorplan of n rooms is encoded to a unique Reduct-Seq of length 3n. Also a decoding algorithm from a Reduct-Seq to a unique floorplan is presented. The computational complexities of encoding and decoding are both only O (n). The number of distinct Reduct-Seq's is counted and revealed that it is not much larger than that of floorplans of the slicing structure. Thus our contribution is to show that the general floorplans can be searched whithout much larger computation cost than that for searching the slicing structure floorplans. Experiments revealed good performances for several circuits. |
| Keyword(in Japanese) | (See Japanese page) |
| Keyword(in English) | floorplan / placement / packing / Reduct-Seq / simulated annealing / rectangular dissection |
| Paper # | CAS2000-15,VLD2000-24,DSP2000-36 |
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| Conference Information | |
| Committee | DSP |
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| Conference Date | 2000/6/15(1days) |
| Place (in Japanese) | (See Japanese page) |
| Place (in English) | |
| Topics (in Japanese) | (See Japanese page) |
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| Vice Chair | |
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| Paper Information | |
| Registration To | Digital Signal Processing (DSP) |
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| Language | ENG |
| Title (in Japanese) | (See Japanese page) |
| Sub Title (in Japanese) | (See Japanese page) |
| Title (in English) | CAS2000-15 / VLD2000-24 / DSP2000-36 A General and Fast Floorplanning by Reduct-Seq Representation |
| Sub Title (in English) | |
| Keyword(1) | floorplan |
| Keyword(2) | placement |
| Keyword(3) | packing |
| Keyword(4) | Reduct-Seq |
| Keyword(5) | simulated annealing |
| Keyword(6) | rectangular dissection |
| 1st Author's Name | Keishi SAKANUSHI |
| 1st Author's Affiliation | Department of Communications and Integrated Systems, Tokyo Institute of Technology() |
| 2nd Author's Name | Kentarou MIDORIKAWA |
| 2nd Author's Affiliation | Department of Communications and Integrated Systems, Tokyo Institute of Technology |
| 3rd Author's Name | Yoji KAJITANI |
| 3rd Author's Affiliation | Department of Communications and Integrated Systems, Tokyo Institute of Technology |
| Date | 2000/6/15 |
| Paper # | CAS2000-15,VLD2000-24,DSP2000-36 |
| Volume (vol) | vol.100 |
| Number (no) | 122 |
| Page | pp.pp.- |
| #Pages | 8 |
| Date of Issue | |