Presentation 2000/6/15
CAS2000-11 / VLD2000-20 / DSP2000-32 Algorithm Studies of BS Digital System Demodulator LSI
Lap Shing Chan, Hiroyuki Mizutani, Kazuya Yamanaka, Shuji Murakami, Hirohisa Machida, Masahiko Nakamura, Eiji Arita, Takashi Fujiwara, Hiroyuki Nakayama, Sumitaka Takeuchi, Masahiko Yoshimoto,
PDF Download Page PDF download Page Link
Abstract(in Japanese) (See Japanese page)
Abstract(in English) The new demodulation algorithm design challenges imposed by the characteristic of BS digital system having composite modulated (8/Q/BPSK) signals in the transmission stream are reported. In brief, dynamically configurable multi-format carrier recovery loop is required in carrier recovery. Conventional Zero-Crossing algorithm using only sign of received signals needs to be modified for implementing timing recovery. In an attempt to achieve better performance on Viterbi soft-decoder, a new hybrid 8PSK de-mapping scheme is to be introduced. Simulations on SPW (Signal Processing Worksystem) showed that carrier recovery convergenece up to ±300kHz frequency offset as well as 0.17dB improvement at BER=1.0E-3 at Viterbi decoder output can be achieved.
Keyword(in Japanese) (See Japanese page)
Keyword(in English) BS Digital TV / Carrier Recovery / Timing Recovery / De-mapping / Demodulator
Paper # CAS2000-11,VLD2000-20,DSP2000-32
Date of Issue

Conference Information
Committee DSP
Conference Date 2000/6/15(1days)
Place (in Japanese) (See Japanese page)
Place (in English)
Topics (in Japanese) (See Japanese page)
Topics (in English)
Chair
Vice Chair
Secretary
Assistant

Paper Information
Registration To Digital Signal Processing (DSP)
Language ENG
Title (in Japanese) (See Japanese page)
Sub Title (in Japanese) (See Japanese page)
Title (in English) CAS2000-11 / VLD2000-20 / DSP2000-32 Algorithm Studies of BS Digital System Demodulator LSI
Sub Title (in English)
Keyword(1) BS Digital TV
Keyword(2) Carrier Recovery
Keyword(3) Timing Recovery
Keyword(4) De-mapping
Keyword(5) Demodulator
1st Author's Name Lap Shing Chan
1st Author's Affiliation System LSI Division, Mitsubishi Electric Corporation()
2nd Author's Name Hiroyuki Mizutani
2nd Author's Affiliation LTEC Corporation
3rd Author's Name Kazuya Yamanaka
3rd Author's Affiliation System LSI Division, Mitsubishi Electric Corporation
4th Author's Name Shuji Murakami
4th Author's Affiliation System LSI Division, Mitsubishi Electric Corporation
5th Author's Name Hirohisa Machida
5th Author's Affiliation System LSI Division, Mitsubishi Electric Corporation
6th Author's Name Masahiko Nakamura
6th Author's Affiliation System LSI Division, Mitsubishi Electric Corporation
7th Author's Name Eiji Arita
7th Author's Affiliation Information Technology R&D Center, Mitsubishi Electric Corporation
8th Author's Name Takashi Fujiwara
8th Author's Affiliation Information Technology R&D Center, Mitsubishi Electric Corporation
9th Author's Name Hiroyuki Nakayama
9th Author's Affiliation Information Technology R&D Center, Mitsubishi Electric Corporation
10th Author's Name Sumitaka Takeuchi
10th Author's Affiliation System LSI Division, Mitsubishi Electric Corporation
11th Author's Name Masahiko Yoshimoto
11th Author's Affiliation Information Technology R&D Center, Mitsubishi Electric Corporation
Date 2000/6/15
Paper # CAS2000-11,VLD2000-20,DSP2000-32
Volume (vol) vol.100
Number (no) 122
Page pp.pp.-
#Pages 8
Date of Issue