| Presentation | 1998/6/26 A Reconfigurable Digital Signal Processor B.K Tan, R Yoshimura, M Ichihashi, T Ogawa, K Taniguchi, |
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| PDF Download Page | PDF download Page Link |
| Abstract(in Japanese) | (See Japanese page) |
| Abstract(in English) | This paper introduces a new architecture based DSP processor, which consists of n×n mesh multiprocessor for digital signal processing.The hardware-based architecture has higher performance compare to traditional microprocessor solution to signal processing without losing much flexibility.The processor has been designed with a large number of process elements to support parallel tasks.The routing flexibility of the array multiprocssor is high enough that the architecture itself is fault tolerant.The new architecture has ben implemented in prototype chip using 0.5μm CMOS process. |
| Keyword(in Japanese) | (See Japanese page) |
| Keyword(in English) | Digital Signal Processing / Reconfigurable / Processor Array / Fault Tolerant |
| Paper # | CAS98-27,VLD98-27,DSP98-56 |
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| Conference Information | |
| Committee | DSP |
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| Conference Date | 1998/6/26(1days) |
| Place (in Japanese) | (See Japanese page) |
| Place (in English) | |
| Topics (in Japanese) | (See Japanese page) |
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| Paper Information | |
| Registration To | Digital Signal Processing (DSP) |
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| Language | JPN |
| Title (in Japanese) | (See Japanese page) |
| Sub Title (in Japanese) | (See Japanese page) |
| Title (in English) | A Reconfigurable Digital Signal Processor |
| Sub Title (in English) | |
| Keyword(1) | Digital Signal Processing |
| Keyword(2) | Reconfigurable |
| Keyword(3) | Processor Array |
| Keyword(4) | Fault Tolerant |
| 1st Author's Name | B.K Tan |
| 1st Author's Affiliation | Department of Electronics and Information Systems Faculty of Engineering, Osaka Univ.() |
| 2nd Author's Name | R Yoshimura |
| 2nd Author's Affiliation | Department of Electronics and Information Systems Faculty of Engineering, Osaka Univ. |
| 3rd Author's Name | M Ichihashi |
| 3rd Author's Affiliation | Department of Electronics and Information Systems Faculty of Engineering, Osaka Univ. |
| 4th Author's Name | T Ogawa |
| 4th Author's Affiliation | Department of Electronics and Information Systems Faculty of Engineering, Osaka Univ. |
| 5th Author's Name | K Taniguchi |
| 5th Author's Affiliation | Department of Electronics and Information Systems Faculty of Engineering, Osaka Univ. |
| Date | 1998/6/26 |
| Paper # | CAS98-27,VLD98-27,DSP98-56 |
| Volume (vol) | vol.98 |
| Number (no) | 144 |
| Page | pp.pp.- |
| #Pages | 7 |
| Date of Issue | |