Presentation 1998/10/15
Parllel Radix-4 FFT Implementation Using SIMD Multimedia Instructions
Kouhei NADEHARA, Takashi MIYAZAKI, Ichiro KURODA,
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Abstract(in English) In this report, an implementation and evaluation of the fast radix-4 complex FFT using 4-parallel SIMD instructions are presented. Four radix-4 butterflies are calculated in parallel following the same signal flow at all stages by loading consecutive 4 elements into a register. At the last stage, every 4 elements is packed into a register and calculated in parallel. The implementation result on the V830R processor, which has a 4-parallel SIMD-type multimedia instuction set, achieves 35% less clock count than the conventional inplementation. Multiply-accumulate instructions with symmetrical rounding introduced to the V830R processor are effective to maintain FFT accuracy.
Keyword(in Japanese) (See Japanese page)
Keyword(in English) SIMD Instruction / FFT / Fast Fourier Transform / Rounding / Error
Paper # DSP98-100,ICD98-187,CPSY98-102
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Conference Information
Committee DSP
Conference Date 1998/10/15(1days)
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Registration To Digital Signal Processing (DSP)
Language JPN
Title (in Japanese) (See Japanese page)
Sub Title (in Japanese) (See Japanese page)
Title (in English) Parllel Radix-4 FFT Implementation Using SIMD Multimedia Instructions
Sub Title (in English)
Keyword(1) SIMD Instruction
Keyword(2) FFT
Keyword(3) Fast Fourier Transform
Keyword(4) Rounding
Keyword(5) Error
1st Author's Name Kouhei NADEHARA
1st Author's Affiliation C&C Media Research Laboratories, NEC Corporation()
2nd Author's Name Takashi MIYAZAKI
2nd Author's Affiliation C&C Media Research Laboratories, NEC Corporation
3rd Author's Name Ichiro KURODA
3rd Author's Affiliation C&C Media Research Laboratories, NEC Corporation
Date 1998/10/15
Paper # DSP98-100,ICD98-187,CPSY98-102
Volume (vol) vol.98
Number (no) 318
Page pp.pp.-
#Pages 8
Date of Issue