| Presentation | 1995/10/19 A 286MHz 64-bit Floating Point Multiplier with Enhanced CG Operation Hiroshi MAKINO, Hiroaki SUZUKI, Hiroyuki MORINAKA, Yasunobu NAKASE, Koichiro MASHIKO, Tadashi SUMI, |
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| PDF Download Page | PDF download Page Link |
| Abstract(in Japanese) | (See Japanese page) |
| Abstract(in English) | This paper presents a high speed 64-bit floating-point (FP) multiplier with a useful function for computer graphics (CG). The critical path delay was minimized by selecting high speed gates and limiting the stage number of series transmission gates (TGs). We implemented the special function of "CG multiplication" that directly multiplies a pixel data by a FP data. The process technology is 0.5-μm CMOS with triple metal. The active area size is 4.2×5.1mm^2. The operating frequency is 286MHz at the supply voltage of 3.3V. Implementation of CG multiplication increases the transistor count only 4%. Also, it has no effect on the delay in the critical path. |
| Keyword(in Japanese) | (See Japanese page) |
| Keyword(in English) | floating point multiplier / critical path / computer graphics / transmission gate / high speed / CM0S |
| Paper # | DSP95-99,ICD95-148 |
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| Conference Information | |
| Committee | DSP |
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| Conference Date | 1995/10/19(1days) |
| Place (in Japanese) | (See Japanese page) |
| Place (in English) | |
| Topics (in Japanese) | (See Japanese page) |
| Topics (in English) | |
| Chair | |
| Vice Chair | |
| Secretary | |
| Assistant | |
| Paper Information | |
| Registration To | Digital Signal Processing (DSP) |
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| Language | JPN |
| Title (in Japanese) | (See Japanese page) |
| Sub Title (in Japanese) | (See Japanese page) |
| Title (in English) | A 286MHz 64-bit Floating Point Multiplier with Enhanced CG Operation |
| Sub Title (in English) | |
| Keyword(1) | floating point multiplier |
| Keyword(2) | critical path |
| Keyword(3) | computer graphics |
| Keyword(4) | transmission gate |
| Keyword(5) | high speed |
| Keyword(6) | CM0S |
| 1st Author's Name | Hiroshi MAKINO |
| 1st Author's Affiliation | System LSI Laboratory, Mitsubishi Electric Corporation() |
| 2nd Author's Name | Hiroaki SUZUKI |
| 2nd Author's Affiliation | System LSI Laboratory, Mitsubishi Electric Corporation |
| 3rd Author's Name | Hiroyuki MORINAKA |
| 3rd Author's Affiliation | System LSI Laboratory, Mitsubishi Electric Corporation |
| 4th Author's Name | Yasunobu NAKASE |
| 4th Author's Affiliation | System LSI Laboratory, Mitsubishi Electric Corporation |
| 5th Author's Name | Koichiro MASHIKO |
| 5th Author's Affiliation | System LSI Laboratory, Mitsubishi Electric Corporation |
| 6th Author's Name | Tadashi SUMI |
| 6th Author's Affiliation | System LSI Laboratory, Mitsubishi Electric Corporation |
| Date | 1995/10/19 |
| Paper # | DSP95-99,ICD95-148 |
| Volume (vol) | vol.95 |
| Number (no) | 298 |
| Page | pp.pp.- |
| #Pages | 8 |
| Date of Issue | |