| Presentation | 1995/10/19 Leading-zero Anticipatory Logic for High-speed Floating Point Addition Hiroaki SUZUKI, Hiroyuki MORINAKA, Hiroshi MAKINO, Yasunobu NAKASE, Koichiro MASHIKO, Tadashi SUMI, |
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| PDF Download Page | PDF download Page Link |
| Abstract(in Japanese) | (See Japanese page) |
| Abstract(in English) | This paper describes a new Leading-Zero Anticipatory (LZA) Logic for high-speed floating-point addition (FADD). This method carries out the pre-decoding for the normalization concurrently with the addition for significant. Besides, it performs the shift operation in parallel with the rounding operation. The proposed logic consists of the simple circuit with l.8% penalty in transistor count. The FADD core using the proposed logic operates at 160MHz, where the core has been fabricated with 0.5μm CMOS technology with triple metal interconnections. |
| Keyword(in Japanese) | (See Japanese page) |
| Keyword(in English) | Floating-Point Arithmetic / Floating-Point Adder Subtractor / Lading-zero Anticipation |
| Paper # | DSP95-98,ICD95-147 |
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| Conference Information | |
| Committee | DSP |
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| Conference Date | 1995/10/19(1days) |
| Place (in Japanese) | (See Japanese page) |
| Place (in English) | |
| Topics (in Japanese) | (See Japanese page) |
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| Paper Information | |
| Registration To | Digital Signal Processing (DSP) |
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| Language | JPN |
| Title (in Japanese) | (See Japanese page) |
| Sub Title (in Japanese) | (See Japanese page) |
| Title (in English) | Leading-zero Anticipatory Logic for High-speed Floating Point Addition |
| Sub Title (in English) | |
| Keyword(1) | Floating-Point Arithmetic |
| Keyword(2) | Floating-Point Adder Subtractor |
| Keyword(3) | Lading-zero Anticipation |
| 1st Author's Name | Hiroaki SUZUKI |
| 1st Author's Affiliation | System LSI Laboratory, Mitsubishi Electric Corporation() |
| 2nd Author's Name | Hiroyuki MORINAKA |
| 2nd Author's Affiliation | System LSI Laboratory, Mitsubishi Electric Corporation |
| 3rd Author's Name | Hiroshi MAKINO |
| 3rd Author's Affiliation | System LSI Laboratory, Mitsubishi Electric Corporation |
| 4th Author's Name | Yasunobu NAKASE |
| 4th Author's Affiliation | System LSI Laboratory, Mitsubishi Electric Corporation |
| 5th Author's Name | Koichiro MASHIKO |
| 5th Author's Affiliation | System LSI Laboratory, Mitsubishi Electric Corporation |
| 6th Author's Name | Tadashi SUMI |
| 6th Author's Affiliation | System LSI Laboratory, Mitsubishi Electric Corporation |
| Date | 1995/10/19 |
| Paper # | DSP95-98,ICD95-147 |
| Volume (vol) | vol.95 |
| Number (no) | 298 |
| Page | pp.pp.- |
| #Pages | 6 |
| Date of Issue | |