| Presentation | 1995/10/19 A 64bit Carry Look-ahead CMOS Adder using Modified Carry Select Hiroyuki Morinaka, Hiroshi Makino, Yasunobu Nakase, Hiroaki Suzuki, Koichiro Mashiko, Tadashi Sumi, |
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| PDF Download Page | PDF download Page Link |
| Abstract(in Japanese) | (See Japanese page) |
| Abstract(in English) | We present a 64-b Carry Look-ahead (CLA) adder using Modified Carry Select(MCS).We derived the optimum structure of the adder from considering both delay and size. The optimization includes the wiring delay and the gate capacitance delay as well as the gate intrinsic delay. MCS has 20% area advantage over the conventional Carry Select Adder. A 2.6ns delay was achieved at 3.3V Power supply using a 0.5-μm CMOS technology. The she is 1305μm x 207μm (0.27mm2). This adder achieves the high speed and small area performance. |
| Keyword(in Japanese) | (See Japanese page) |
| Keyword(in English) | Addition / Carry Look-ahead / Binary Look-ahead / Modified Carry Select |
| Paper # | DSP95-97,ICD95-146 |
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| Conference Information | |
| Committee | DSP |
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| Conference Date | 1995/10/19(1days) |
| Place (in Japanese) | (See Japanese page) |
| Place (in English) | |
| Topics (in Japanese) | (See Japanese page) |
| Topics (in English) | |
| Chair | |
| Vice Chair | |
| Secretary | |
| Assistant | |
| Paper Information | |
| Registration To | Digital Signal Processing (DSP) |
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| Language | JPN |
| Title (in Japanese) | (See Japanese page) |
| Sub Title (in Japanese) | (See Japanese page) |
| Title (in English) | A 64bit Carry Look-ahead CMOS Adder using Modified Carry Select |
| Sub Title (in English) | |
| Keyword(1) | Addition |
| Keyword(2) | Carry Look-ahead |
| Keyword(3) | Binary Look-ahead |
| Keyword(4) | Modified Carry Select |
| 1st Author's Name | Hiroyuki Morinaka |
| 1st Author's Affiliation | ADVANCED CIRCUIT DESIGN SECTION LSI DEVELOPMENT DEPT.(B) MITSUBISHI ELECTRIC CORPORATION SYSTEM LSI LABORATORY() |
| 2nd Author's Name | Hiroshi Makino |
| 2nd Author's Affiliation | ADVANCED CIRCUIT DESIGN SECTION LSI DEVELOPMENT DEPT.(B) MITSUBISHI ELECTRIC CORPORATION SYSTEM LSI LABORATORY |
| 3rd Author's Name | Yasunobu Nakase |
| 3rd Author's Affiliation | ADVANCED CIRCUIT DESIGN SECTION LSI DEVELOPMENT DEPT.(B) MITSUBISHI ELECTRIC CORPORATION SYSTEM LSI LABORATORY |
| 4th Author's Name | Hiroaki Suzuki |
| 4th Author's Affiliation | ADVANCED CIRCUIT DESIGN SECTION LSI DEVELOPMENT DEPT.(B) MITSUBISHI ELECTRIC CORPORATION SYSTEM LSI LABORATORY |
| 5th Author's Name | Koichiro Mashiko |
| 5th Author's Affiliation | ADVANCED CIRCUIT DESIGN SECTION LSI DEVELOPMENT DEPT.(B) MITSUBISHI ELECTRIC CORPORATION SYSTEM LSI LABORATORY |
| 6th Author's Name | Tadashi Sumi |
| 6th Author's Affiliation | ADVANCED CIRCUIT DESIGN SECTION LSI DEVELOPMENT DEPT.(B) MITSUBISHI ELECTRIC CORPORATION SYSTEM LSI LABORATORY |
| Date | 1995/10/19 |
| Paper # | DSP95-97,ICD95-146 |
| Volume (vol) | vol.95 |
| Number (no) | 298 |
| Page | pp.pp.- |
| #Pages | 6 |
| Date of Issue | |