| Presentation | 1997/6/27 A Simultaneous Placement and Global Routing Algorithm for FPGAs with Power Optimization Kaoru UKAI, Nozomu TOGAWA, Masao SATO, Tatsuo OHTSUKI, |
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| PDF Download Page | PDF download Page Link |
| Abstract(in Japanese) | (See Japanese page) |
| Abstract(in English) | FPGAs are becoming used as interfaces which connect core chips and peripheral LSIs, that can increase the flexibility of system LSIs. Since FPGAs consume more power than conventional gate arrays, a design methodology with power optimization is required for FPGAs in order to reduce power consumption in the entire system LSIs. In this paper, we propose a simultaneous placement and global routing algorithm for FPGAs with power optimization. The algorithm is based on hierarchical bipartitioning of layout regions and sets of logic-blocks to be placed. If there exist connections between bipatitioned logic-block sets, pairs of pseudo-blocks are introduced to preserve the connections. A global route is represented by a sequence of pseudo-blocks. Since pseudo-blocks and logic-blocks can be dealt with equally, placement and global routing are processed simultaneously. The algorithm attaches weights to the nets with high switching activities and assignes the blocks connected by weighted nets to the same region. Thus their length is shortened and power consumption of a whole circuit can be reduced. The experimental results demonstrate the efficiency and effectiveness of the algorithm. |
| Keyword(in Japanese) | (See Japanese page) |
| Keyword(in English) | FPGA / low power layout design / placement / global routinq / switching activity / wire capacitance |
| Paper # | CAS97-42 |
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| Conference Information | |
| Committee | DSP |
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| Conference Date | 1997/6/27(1days) |
| Place (in Japanese) | (See Japanese page) |
| Place (in English) | |
| Topics (in Japanese) | (See Japanese page) |
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| Paper Information | |
| Registration To | Digital Signal Processing (DSP) |
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| Language | JPN |
| Title (in Japanese) | (See Japanese page) |
| Sub Title (in Japanese) | (See Japanese page) |
| Title (in English) | A Simultaneous Placement and Global Routing Algorithm for FPGAs with Power Optimization |
| Sub Title (in English) | |
| Keyword(1) | FPGA |
| Keyword(2) | low power layout design |
| Keyword(3) | placement |
| Keyword(4) | global routinq |
| Keyword(5) | switching activity |
| Keyword(6) | wire capacitance |
| 1st Author's Name | Kaoru UKAI |
| 1st Author's Affiliation | Dept. of Electronics, Information and Communication Engineering Waseda University() |
| 2nd Author's Name | Nozomu TOGAWA |
| 2nd Author's Affiliation | Dept. of Electronics, Information and Communication Engineering Waseda University |
| 3rd Author's Name | Masao SATO |
| 3rd Author's Affiliation | Dept. of Electronics, Information and Communication Engineering Waseda University |
| 4th Author's Name | Tatsuo OHTSUKI |
| 4th Author's Affiliation | Dept. of Electronics, Information and Communication Engineering Waseda University |
| Date | 1997/6/27 |
| Paper # | CAS97-42 |
| Volume (vol) | vol.97 |
| Number (no) | 141 |
| Page | pp.pp.- |
| #Pages | 8 |
| Date of Issue | |