Presentation 1997/6/27
A PLD Design of Self-Organizing Network
Jun'ya Ohkubo, Yoshikazu Miyanaga, Koji Tochinai,
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Abstract(in English) This report presents a hardware design of a high-speed processing chip in which a self-organizing clustering system is implemented. The I/O dimension and the node number of the system proposed in this report are programmable. We introduce pipeline processing into this system to increase speed and use pipeline operators in every basic element. An algorithm in which the total number of the states is reduced is developed in order to design compactly and improve the efficiency of the PLD implementation. In this paper, we explore the performance of the system under the condition that it can be realized by using an actual PLD. Therefore, we designed the circuit within 23,000 gates.
Keyword(in Japanese) (See Japanese page)
Keyword(in English) Self-Organizing Clustering / Pipeline Processing / PLD
Paper # CAS97-33
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Conference Information
Committee DSP
Conference Date 1997/6/27(1days)
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Registration To Digital Signal Processing (DSP)
Language JPN
Title (in Japanese) (See Japanese page)
Sub Title (in Japanese) (See Japanese page)
Title (in English) A PLD Design of Self-Organizing Network
Sub Title (in English)
Keyword(1) Self-Organizing Clustering
Keyword(2) Pipeline Processing
Keyword(3) PLD
1st Author's Name Jun'ya Ohkubo
1st Author's Affiliation Graduate School of Engineering, Hokkaido University()
2nd Author's Name Yoshikazu Miyanaga
2nd Author's Affiliation Graduate School of Engineering, Hokkaido University
3rd Author's Name Koji Tochinai
3rd Author's Affiliation Graduate School of Engineering, Hokkaido University
Date 1997/6/27
Paper # CAS97-33
Volume (vol) vol.97
Number (no) 141
Page pp.pp.-
#Pages 6
Date of Issue