Presentation 2002/1/23
A Multiple-Valued Logic and Memory with Merged Single-Electron and MOS Transistors
Hiroshi INOKAWA, Akira FUJIWARA, Yasuo TAKAHASHI,
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Abstract(in English) We propose merged single-electron and MOS devices that serve as basic components of multiple-valued logic, such as a universal literal gate and a quantizer. We verified their operation by using single-electron transistors and MOSFETs fabricated on the same wafer by pattern-dependent oxidation of silicon. We also discuss their application to a multiple-valued static memory, an analog-to-digital converter and a multiple-valued adder.
Keyword(in Japanese) (See Japanese page)
Keyword(in English) single-electron transistor / SET / MOSFET / multiple-valued logic / multiple-valued memory / literal gate / quantizer
Paper # 2001-ED-247,2001-SDM-250
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Committee ED
Conference Date 2002/1/23(1days)
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Language JPN
Title (in Japanese) (See Japanese page)
Sub Title (in Japanese) (See Japanese page)
Title (in English) A Multiple-Valued Logic and Memory with Merged Single-Electron and MOS Transistors
Sub Title (in English)
Keyword(1) single-electron transistor
Keyword(2) SET
Keyword(3) MOSFET
Keyword(4) multiple-valued logic
Keyword(5) multiple-valued memory
Keyword(6) literal gate
Keyword(7) quantizer
1st Author's Name Hiroshi INOKAWA
1st Author's Affiliation NTT Basic Research Laboratories, NTT Corporation()
2nd Author's Name Akira FUJIWARA
2nd Author's Affiliation NTT Basic Research Laboratories, NTT Corporation
3rd Author's Name Yasuo TAKAHASHI
3rd Author's Affiliation NTT Basic Research Laboratories, NTT Corporation
Date 2002/1/23
Paper # 2001-ED-247,2001-SDM-250
Volume (vol) vol.101
Number (no) 619
Page pp.pp.-
#Pages 6
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