Presentation 2002/1/10
Design of Gate Bias Circuit for Compensation of Temperature Dependence and Process Variation of Low Noise Amplifier Using Temperature and Bias Dependent Small Signal FET Model
Koji YAMANAKA, Kazuhisa YAMAUCHI, Kazutomi MORI, Yukio IKEDA, Hiroshi IKEMATSU, Naoki TANAHASHI, Tadashi TAKAGI,
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Abstract(in English) In this paper, a Ku-band Low-Noise MMIC amplifier is presented, which is equipped with a bias circuit that compensates not only temperature dependence of FETs' gain but also gain variation between chips due to process variations. The Ku-band low noise MMIC amplifier with proposed gate-bias circuit was designed and manufactured. It was proved that the proposed bias circuit reduced the temperature dependence of the two-stage MMIC amplifier's gain from 1.4dB/100K to 1.0dB/100K. The chip area consumed for the bias circuit is less than 10% of the total chip size of 1.17mm^2. The gain variation between chips was reduced to 0.25dB in RMS. This amplifier is suitable for active phased array applications.
Keyword(in Japanese) (See Japanese page)
Keyword(in English) Low Noise Amplifier / MMIC / Bias Circuit / Temperature Dependence / Process Variation / Active Phased Array Antenna
Paper # 2001-ED-206,2001-MW-161,2001-ICD-203
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Committee ED
Conference Date 2002/1/10(1days)
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Language JPN
Title (in Japanese) (See Japanese page)
Sub Title (in Japanese) (See Japanese page)
Title (in English) Design of Gate Bias Circuit for Compensation of Temperature Dependence and Process Variation of Low Noise Amplifier Using Temperature and Bias Dependent Small Signal FET Model
Sub Title (in English)
Keyword(1) Low Noise Amplifier
Keyword(2) MMIC
Keyword(3) Bias Circuit
Keyword(4) Temperature Dependence
Keyword(5) Process Variation
Keyword(6) Active Phased Array Antenna
1st Author's Name Koji YAMANAKA
1st Author's Affiliation Mitsubishi Electric Corporation Information Technology R&D Center()
2nd Author's Name Kazuhisa YAMAUCHI
2nd Author's Affiliation Mitsubishi Electric Corporation Information Technology R&D Center
3rd Author's Name Kazutomi MORI
3rd Author's Affiliation Mitsubishi Electric Corporation Information Technology R&D Center
4th Author's Name Yukio IKEDA
4th Author's Affiliation Mitsubishi Electric Corporation Information Technology R&D Center
5th Author's Name Hiroshi IKEMATSU
5th Author's Affiliation Mitsubishi Electric Corporation Information Technology R&D Center
6th Author's Name Naoki TANAHASHI
6th Author's Affiliation Mitsubishi Electric Corporation Information Technology R&D Center
7th Author's Name Tadashi TAKAGI
7th Author's Affiliation Mitsubishi Electric Corporation Information Technology R&D Center
Date 2002/1/10
Paper # 2001-ED-206,2001-MW-161,2001-ICD-203
Volume (vol) vol.101
Number (no) 550
Page pp.pp.-
#Pages 6
Date of Issue