| Presentation | 2001/6/29 Effects of Bi Content on Electrical Properties of Pt/SrBi_2Nb_2O_9/Si Ferroelectric Gate Structure Hoon Sang Choi, Jin Shi Zhao, Yong Tae Kim, Kwan Lee, Jong-Han Lee, Seong-Il Kim, In-Hoon Choi, |
|---|---|
| PDF Download Page | PDF download Page Link |
| Abstract(in Japanese) | (See Japanese page) |
| Abstract(in English) | We have investigated effects of Bi content on electrical properties of SrBi_2Nb_2O_9(SBN) thin films. The SBN films were deposited with co-sputtering method in situ on p-type Si (100) substrates. In order to control the Bi/Sr content ratio, we used SrNb_2O_6 and Bi_2O_3 targets with different powers of RF magnetrons. We have found that electrical properties are strongly sensitive to the Bi content. The memory window gradually increased with increasing the Bi/Sr ratio in the SBN thin films, but when the Bi/Sr ratio was over 3.1 the electrical properties such as memory window and breakdown voltage were degraded. The memory window of the Pt/SBN/Si ferroelectric gate structure with the Bi/Sr ratio of 3.1 was 1.8 V ar applied voltage of 3V. And the leakage current density was 4.74×10^<-8> A/cm^2 at applied voltage of 3V. |
| Keyword(in Japanese) | (See Japanese page) |
| Keyword(in English) | SrBi_2Nb_2O_9 / memory window / ferroelectric gate structure |
| Paper # | ED2001-88, SDM2001-95 |
| Date of Issue |
| Conference Information | |
| Committee | ED |
|---|---|
| Conference Date | 2001/6/29(1days) |
| Place (in Japanese) | (See Japanese page) |
| Place (in English) | |
| Topics (in Japanese) | (See Japanese page) |
| Topics (in English) | |
| Chair | |
| Vice Chair | |
| Secretary | |
| Assistant | |
| Paper Information | |
| Registration To | Electron Devices (ED) |
|---|---|
| Language | ENG |
| Title (in Japanese) | (See Japanese page) |
| Sub Title (in Japanese) | (See Japanese page) |
| Title (in English) | Effects of Bi Content on Electrical Properties of Pt/SrBi_2Nb_2O_9/Si Ferroelectric Gate Structure |
| Sub Title (in English) | |
| Keyword(1) | SrBi_2Nb_2O_9 |
| Keyword(2) | memory window |
| Keyword(3) | ferroelectric gate structure |
| 1st Author's Name | Hoon Sang Choi |
| 1st Author's Affiliation | Division of Materials Science and Engineering, Korea University() |
| 2nd Author's Name | Jin Shi Zhao |
| 2nd Author's Affiliation | Division of Materials Science and Engineering, Korea University |
| 3rd Author's Name | Yong Tae Kim |
| 3rd Author's Affiliation | Semiconductor Device Lab., Korea Institute of Science and Technology |
| 4th Author's Name | Kwan Lee |
| 4th Author's Affiliation | Division of Materials Science and Engineering, Korea University |
| 5th Author's Name | Jong-Han Lee |
| 5th Author's Affiliation | Division of Materials Science and Engineering, Korea University |
| 6th Author's Name | Seong-Il Kim |
| 6th Author's Affiliation | Semiconductor Device Lab., Korea Institute of Science and Technology |
| 7th Author's Name | In-Hoon Choi |
| 7th Author's Affiliation | Division of Materials Science and Engineering, Korea University |
| Date | 2001/6/29 |
| Paper # | ED2001-88, SDM2001-95 |
| Volume (vol) | vol.101 |
| Number (no) | 161 |
| Page | pp.pp.- |
| #Pages | 6 |
| Date of Issue | |