| Presentation | 2000/6/21 ED2000-46 / SDM2000-46 Analysis of a High Performance Self-Aligned Elevated Source Drain MOSFET with Reduced Gate-Induced Drain-Leakage Kyung-Whan Kim, Chang-Soon Choi, Woo-Young Choi, |
|---|---|
| PDF Download Page | PDF download Page Link |
| Abstract(in Japanese) | (See Japanese page) |
| Abstract(in English) | A novel self-aligned ESD(Elevated Source Drain) MOSFET structure which can effectively reduce the GIDL(Gate-Induced Drain Leakage) current is proposed and analyzed. The proposed ESD structure is characterized by sidewall spacer width and recessed-channel depth which are determined by dry-etching process. Elevation of the Source/Drain extension region is realized so that the low-activation effect caused by low-energy ion implantation can be avoided. Unlike the conventional LDD structures, it is shown that the GIDL current of the ESD structure is suppressed without sacrificing the maximum driving capability. The main reason for the reduction of GIDL current is the decreased electric field at the point of the maximum band-to-band tunneling as the peak electric field is shifted toward the drain side. |
| Keyword(in Japanese) | (See Japanese page) |
| Keyword(in English) | self-aligned / ESD MOSFET / GIDL / dry-etching / low-activation effect / peak electric field |
| Paper # | ED2000-46,SDM2000-46 |
| Date of Issue |
| Conference Information | |
| Committee | ED |
|---|---|
| Conference Date | 2000/6/21(1days) |
| Place (in Japanese) | (See Japanese page) |
| Place (in English) | |
| Topics (in Japanese) | (See Japanese page) |
| Topics (in English) | |
| Chair | |
| Vice Chair | |
| Secretary | |
| Assistant | |
| Paper Information | |
| Registration To | Electron Devices (ED) |
|---|---|
| Language | ENG |
| Title (in Japanese) | (See Japanese page) |
| Sub Title (in Japanese) | (See Japanese page) |
| Title (in English) | ED2000-46 / SDM2000-46 Analysis of a High Performance Self-Aligned Elevated Source Drain MOSFET with Reduced Gate-Induced Drain-Leakage |
| Sub Title (in English) | |
| Keyword(1) | self-aligned |
| Keyword(2) | ESD MOSFET |
| Keyword(3) | GIDL |
| Keyword(4) | dry-etching |
| Keyword(5) | low-activation effect |
| Keyword(6) | peak electric field |
| 1st Author's Name | Kyung-Whan Kim |
| 1st Author's Affiliation | Electrical and Computer Engineering, Yonsei University() |
| 2nd Author's Name | Chang-Soon Choi |
| 2nd Author's Affiliation | Electrical and Computer Engineering, Yonsei University |
| 3rd Author's Name | Woo-Young Choi |
| 3rd Author's Affiliation | Electrical and Computer Engineering, Yonsei University |
| Date | 2000/6/21 |
| Paper # | ED2000-46,SDM2000-46 |
| Volume (vol) | vol.100 |
| Number (no) | 147 |
| Page | pp.pp.- |
| #Pages | 6 |
| Date of Issue | |