Presentation 1999/7/23
Electrical Properties of Pt/SrBi_2Ta_2O_9/Pt/SiO_2/Si MFMIS Structures and FETs with Various Area Ratios of MFM capacitor to Pt Floating Gate
Eisuke Tokumitsu, Atsuhiro Amano, Gen Fujii, Hiroshi Ishiwara,
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Abstract(in English) We report the fabrication and characterization of Pt/SrBi_2Ta_2O_9/Pt/SiO_2/Si MFMIS structures and FETs. The area ratio of the Pt/SrBi_2Ta_2O_9/Pt MFM capacitor to the Pt/SiO_2/Si MIS structure is varied from 1:10 to 1:10. It is found that by using a small MFM capacitor on a large MIS structure, a large memory window more than 4 V and a long data retention time can be obtained. Furthermore, non-volatile memory operations of Pt/SrBi_2Ta_2O_9/Pt/SiO_2/Si MFMIS-FETs is demonstrated.
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Keyword(in English) ferroelectric memory / ferroelectric-gate transisitor / MFMISFET / SrBi_2Ta_2O_9
Paper # ED99-121
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Committee ED
Conference Date 1999/7/23(1days)
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Language ENG
Title (in Japanese) (See Japanese page)
Sub Title (in Japanese) (See Japanese page)
Title (in English) Electrical Properties of Pt/SrBi_2Ta_2O_9/Pt/SiO_2/Si MFMIS Structures and FETs with Various Area Ratios of MFM capacitor to Pt Floating Gate
Sub Title (in English)
Keyword(1) ferroelectric memory
Keyword(2) ferroelectric-gate transisitor
Keyword(3) MFMISFET
Keyword(4) SrBi_2Ta_2O_9
1st Author's Name Eisuke Tokumitsu
1st Author's Affiliation Precision & Intelligence Laboratory, Tokyo Institute of Technology()
2nd Author's Name Atsuhiro Amano
2nd Author's Affiliation Frontier Collaborative Research Center, Tokyo Institute of Technology
3rd Author's Name Gen Fujii
3rd Author's Affiliation Frontier Collaborative Research Center, Tokyo Institute of Technology
4th Author's Name Hiroshi Ishiwara
4th Author's Affiliation Precision & Intelligence Laboratory, Tokyo Institute of Technology:Frontier Collaborative Research Center, Tokyo Institute of Technology
Date 1999/7/23
Paper # ED99-121
Volume (vol) vol.99
Number (no) 230
Page pp.pp.-
#Pages 6
Date of Issue