Presentation	1999/7/22 IP Interface Design Experiences with an On-Chip Bus Kyoung-Son Jhang, Joo-Byung Joo, Nak-Woong Eum, Inhag Park,
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Abstract(in English)	Integration of IP cores through an on-chip bus is a process of converting IP communication protocols to a common bus protocol. To integrate IP cores it is necessary to design interface circuits between those cores and the master or slave bus interface. In addition, memory spaces should be allocated for the transactions to the slave cores in the interface design process. This paper presents some empirical considerations on IP interface design for an on-chip PI bus.
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Paper #	ED99-92
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Conference Information
Committee	ED
Conference Date	1999/7/22(1days)
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Registration To	Electron Devices (ED)
Language	ENG
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Title (in English)	IP Interface Design Experiences with an On-Chip Bus
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1st Author's Name	Kyoung-Son Jhang
1st Author's Affiliation	Hannam University()
2nd Author's Name	Joo-Byung Joo
2nd Author's Affiliation	Electronics and Telecommunications Research Institute
3rd Author's Name	Nak-Woong Eum
3rd Author's Affiliation	Electronics and Telecommunications Research Institute
4th Author's Name	Inhag Park
4th Author's Affiliation	Electronics and Telecommunications Research Institute
Date	1999/7/22
Paper #	ED99-92
Volume (vol)	vol.99
Number (no)	229
Page	pp.pp.-
#Pages	6
Date of Issue