| Presentation | 1999/7/22 Reuse Design of Run Length Coder using VHDL Seongmo Park, Seongmin Kim, Inhag Park, Jinjong Cha, Hanjin Cho, |
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| PDF Download Page | PDF download Page Link |
| Abstract(in Japanese) | (See Japanese page) |
| Abstract(in English) | In this paper, we describe the interface specification and core block design methods for Run Length Coder of video compression application. It offers high performance and many features to meet multimedia, and digital video applications. We design VLSI architecture of run length coder using VHDL. This design can achieve the high performance for video coder, is based on H.263 Recommendation. The format of the outputs is compatible with the stream of the Variable Length Coding. Run Length Coder is implemented by register transfer level(RTL) of VHDL. The designed block is synthesized by Compass synthesis with 0.5um CMOS, 3.3V, technology and reuse as core IP(Intellectual Property) of H.263 and MPEG4 application. The run length coder block contains 4,000 logic gates and total 1,536 bits of Static RAM. The designed block is synthesized by Compass synthesis with 0.5μm CMOS, 3.3V, technology. Fully synchronous design allows for fast operation while maintaining a low gate count. The core will reuse to multimedia system and digital video applications. |
| Keyword(in Japanese) | (See Japanese page) |
| Keyword(in English) | |
| Paper # | ED99-90 |
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| Conference Information | |
| Committee | ED |
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| Conference Date | 1999/7/22(1days) |
| Place (in Japanese) | (See Japanese page) |
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| Topics (in Japanese) | (See Japanese page) |
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| Paper Information | |
| Registration To | Electron Devices (ED) |
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| Language | ENG |
| Title (in Japanese) | (See Japanese page) |
| Sub Title (in Japanese) | (See Japanese page) |
| Title (in English) | Reuse Design of Run Length Coder using VHDL |
| Sub Title (in English) | |
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| 1st Author's Name | Seongmo Park |
| 1st Author's Affiliation | Department of Integrated Circuits Design, Electronics and Telecommunications Research Institute() |
| 2nd Author's Name | Seongmin Kim |
| 2nd Author's Affiliation | Department of Integrated Circuits Design, Electronics and Telecommunications Research Institute |
| 3rd Author's Name | Inhag Park |
| 3rd Author's Affiliation | Department of Integrated Circuits Design, Electronics and Telecommunications Research Institute |
| 4th Author's Name | Jinjong Cha |
| 4th Author's Affiliation | Department of Integrated Circuits Design, Electronics and Telecommunications Research Institute |
| 5th Author's Name | Hanjin Cho |
| 5th Author's Affiliation | Department of Integrated Circuits Design, Electronics and Telecommunications Research Institute |
| Date | 1999/7/22 |
| Paper # | ED99-90 |
| Volume (vol) | vol.99 |
| Number (no) | 229 |
| Page | pp.pp.- |
| #Pages | 5 |
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