| Presentation | 1999/7/22 A Reconfigurable Digital Signal Processor B.K. Tan, R. Yoshimura, K. Taniguchi, |
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| PDF Download Page | PDF download Page Link |
| Abstract(in Japanese) | (See Japanese page) |
| Abstract(in English) | This paper introduces a new architecture based DSP processor, which consists of n x n mesh multiprocessor for digital signal processing. All processors are interconnected by a newly designed interconnection network which poses high routing flexibility and broadcasting ability. With large number of processing elements (processors) and high routing flexibility (interconnection network), pipelining and parallel processing can be achieved. Thus, this new architecture paradigm is believed to have better performance compare to traditional microprocessor solution to signal processing without losing much flexibility. In addition, the proposed architecture is fault tolerant. The new architecture has been implemented in a prototype chip using a 0.5-micrometer process. |
| Keyword(in Japanese) | (See Japanese page) |
| Keyword(in English) | Digital Signal Processing / Reconfigurable / Processor Array / Fault Tolerant |
| Paper # | ED99-88 |
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| Conference Information | |
| Committee | ED |
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| Conference Date | 1999/7/22(1days) |
| Place (in Japanese) | (See Japanese page) |
| Place (in English) | |
| Topics (in Japanese) | (See Japanese page) |
| Topics (in English) | |
| Chair | |
| Vice Chair | |
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| Assistant | |
| Paper Information | |
| Registration To | Electron Devices (ED) |
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| Language | ENG |
| Title (in Japanese) | (See Japanese page) |
| Sub Title (in Japanese) | (See Japanese page) |
| Title (in English) | A Reconfigurable Digital Signal Processor |
| Sub Title (in English) | |
| Keyword(1) | Digital Signal Processing |
| Keyword(2) | Reconfigurable |
| Keyword(3) | Processor Array |
| Keyword(4) | Fault Tolerant |
| 1st Author's Name | B.K. Tan |
| 1st Author's Affiliation | Department of Electronics and Information Systems Faculty of Engineering, Osaka Univ.() |
| 2nd Author's Name | R. Yoshimura |
| 2nd Author's Affiliation | Department of Electronics and Information Systems Faculty of Engineering, Osaka Univ. |
| 3rd Author's Name | K. Taniguchi |
| 3rd Author's Affiliation | Department of Electronics and Information Systems Faculty of Engineering, Osaka Univ. |
| Date | 1999/7/22 |
| Paper # | ED99-88 |
| Volume (vol) | vol.99 |
| Number (no) | 229 |
| Page | pp.pp.- |
| #Pages | 7 |
| Date of Issue | |