Presentation | 1999/7/22 A Hardware Cost Estimation Method For Design Reuse Wonjong Kim, Hyunchul Shin, |
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PDF Download Page | PDF download Page Link |
Abstract(in Japanese) | (See Japanese page) |
Abstract(in English) | In this paper, we describe a hardware cost estimation methodology for designs with hard IPs, soft IPs, and gate-level netlists. It is based on a hierarchical floorplanning method which uses a hierarchical partitioning and placement improvement by using the region refinement algorithm. If the given circuit has large soft IPs, we partition them for efficient and flexible floorplanning. At each level of the hierarchy, routing area estimation is performed. Experimental results show that our estimation method is promising. |
Keyword(in Japanese) | (See Japanese page) |
Keyword(in English) | Intellectual Property / design reuse / cost estimation / partitioning / floorplanning |
Paper # | ED99-87 |
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Committee | ED |
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Conference Date | 1999/7/22(1days) |
Place (in Japanese) | (See Japanese page) |
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Topics (in Japanese) | (See Japanese page) |
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Paper Information | |
Registration To | Electron Devices (ED) |
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Language | ENG |
Title (in Japanese) | (See Japanese page) |
Sub Title (in Japanese) | (See Japanese page) |
Title (in English) | A Hardware Cost Estimation Method For Design Reuse |
Sub Title (in English) | |
Keyword(1) | Intellectual Property |
Keyword(2) | design reuse |
Keyword(3) | cost estimation |
Keyword(4) | partitioning |
Keyword(5) | floorplanning |
1st Author's Name | Wonjong Kim |
1st Author's Affiliation | School of Electrical Engineering & Computer Science, Hanyang University() |
2nd Author's Name | Hyunchul Shin |
2nd Author's Affiliation | School of Electrical Engineering & Computer Science, Hanyang University |
Date | 1999/7/22 |
Paper # | ED99-87 |
Volume (vol) | vol.99 |
Number (no) | 229 |
Page | pp.pp.- |
#Pages | 5 |
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