| Presentation | 1999/7/22 Ultra-Low Energy Ion Implant Profile Prediction for sub 0.1μm Technologies Jeong-Won KANG, Young-Ghik Lee, Ki-Ryang Byun, Jea-Hoon Choi, Oh-Keun Kwon, Ho-Jung Hwang, |
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| PDF Download Page | PDF download Page Link |
| Abstract(in Japanese) | (See Japanese page) |
| Abstract(in English) | In this paper, we present the phenomenological local damage accumulation model and results of highly efficient molecular dynamics simulation. Proposed local damage accumulation model is composed by deposited energy, history of recoil event and heat conductance in a cell, and also considers effects of self-relaxation and self-recombination. The results of MDRANGE with local damage accumulation model agree with the experimental results and results of other simulation. We also simulated various doses and various ultra-low energies boron and arsenic ion implantation and dopant distribution for sub 0.1 μm technologies in real space. We obtained dopant profiles by real Ton number corresponding to dose on 0.1 μm × 0.1μm silicon surface in the <100> channeling direction. In the cases of both B and As, as ion dose and implant energy increase, dopant profiles are much affected by locally accumulated damage. Especially, dopant profiles are much influenced by locally accumulated damage at doses above 10^<14>/cm^2 regardless of implant energy. |
| Keyword(in Japanese) | (See Japanese page) |
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| Paper # | ED99-84 |
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| Committee | ED |
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| Conference Date | 1999/7/22(1days) |
| Place (in Japanese) | (See Japanese page) |
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| Topics (in Japanese) | (See Japanese page) |
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| Registration To | Electron Devices (ED) |
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| Language | ENG |
| Title (in Japanese) | (See Japanese page) |
| Sub Title (in Japanese) | (See Japanese page) |
| Title (in English) | Ultra-Low Energy Ion Implant Profile Prediction for sub 0.1μm Technologies |
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| 1st Author's Name | Jeong-Won KANG |
| 1st Author's Affiliation | Semiconductor Process and Device Laboratory, Dept. of Electronic Engineering, Chung-Ang University() |
| 2nd Author's Name | Young-Ghik Lee |
| 2nd Author's Affiliation | Semiconductor Process and Device Laboratory, Dept. of Electronic Engineering, Chung-Ang University |
| 3rd Author's Name | Ki-Ryang Byun |
| 3rd Author's Affiliation | Semiconductor Process and Device Laboratory, Dept. of Electronic Engineering, Chung-Ang University |
| 4th Author's Name | Jea-Hoon Choi |
| 4th Author's Affiliation | Semiconductor Process and Device Laboratory, Dept. of Electronic Engineering, Chung-Ang University |
| 5th Author's Name | Oh-Keun Kwon |
| 5th Author's Affiliation | Semiconductor Process and Device Laboratory, Dept. of Electronic Engineering, Chung-Ang University |
| 6th Author's Name | Ho-Jung Hwang |
| 6th Author's Affiliation | Semiconductor Process and Device Laboratory, Dept. of Electronic Engineering, Chung-Ang University |
| Date | 1999/7/22 |
| Paper # | ED99-84 |
| Volume (vol) | vol.99 |
| Number (no) | 229 |
| Page | pp.pp.- |
| #Pages | 5 |
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