| Presentation | 1999/6/25 A 1.9-ns 10 Port SRAM Macro using STS (Super Time Sharing) Techniques. Takatoshi TAMURA, Yuuji YANAGISAWA, Yasushi SHIMONO, Masami HASEGAWA, Yoshio IIOKA, Takashi IKEWAKI, Yayoi HAYASHI, Yoichi SATO, Makio UCHIDA, |
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| PDF Download Page | PDF download Page Link |
| Abstract(in Japanese) | (See Japanese page) |
| Abstract(in English) | We have developed a 1.9-ns access 512 word-9bit, 10 port (with 5 read ports and 5 write ports) SRAM macro carried on ASIC for multimedia systems. To acheive the higher speed and smaller macro size, a technology called S__-uper T__-ime S__-haring SRAM (STS), which access simultaneously three core composed of 0.35um CMOS, 2 port sub macro is proposed. It is acheived high speed of 1.9-ns clock access time, 5.7-ns cycle time and small macro size of 2,090um×1,640um. |
| Keyword(in Japanese) | (See Japanese page) |
| Keyword(in English) | ASIC / multi port RAM / 10 port RAM / parallel processing / multimedia |
| Paper # | ED99-70 |
| Date of Issue |
| Conference Information | |
| Committee | ED |
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| Conference Date | 1999/6/25(1days) |
| Place (in Japanese) | (See Japanese page) |
| Place (in English) | |
| Topics (in Japanese) | (See Japanese page) |
| Topics (in English) | |
| Chair | |
| Vice Chair | |
| Secretary | |
| Assistant | |
| Paper Information | |
| Registration To | Electron Devices (ED) |
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| Language | JPN |
| Title (in Japanese) | (See Japanese page) |
| Sub Title (in Japanese) | (See Japanese page) |
| Title (in English) | A 1.9-ns 10 Port SRAM Macro using STS (Super Time Sharing) Techniques. |
| Sub Title (in English) | |
| Keyword(1) | ASIC |
| Keyword(2) | multi port RAM |
| Keyword(3) | 10 port RAM |
| Keyword(4) | parallel processing |
| Keyword(5) | multimedia |
| 1st Author's Name | Takatoshi TAMURA |
| 1st Author's Affiliation | Hitachi ULSI Systems Ltd.() |
| 2nd Author's Name | Yuuji YANAGISAWA |
| 2nd Author's Affiliation | Hitachi ULSI Systems Ltd. |
| 3rd Author's Name | Yasushi SHIMONO |
| 3rd Author's Affiliation | Hitachi ULSI Systems Ltd. |
| 4th Author's Name | Masami HASEGAWA |
| 4th Author's Affiliation | Hitachi ULSI Systems Ltd. |
| 5th Author's Name | Yoshio IIOKA |
| 5th Author's Affiliation | Hitachi ULSI Systems Ltd. |
| 6th Author's Name | Takashi IKEWAKI |
| 6th Author's Affiliation | Hitachi ULSI Systems Ltd. |
| 7th Author's Name | Yayoi HAYASHI |
| 7th Author's Affiliation | Hitachi ULSI Systems Ltd. |
| 8th Author's Name | Yoichi SATO |
| 8th Author's Affiliation | Hitachi ULSI Systems Ltd. |
| 9th Author's Name | Makio UCHIDA |
| 9th Author's Affiliation | Device Development Center , Hitachi Ltd. |
| Date | 1999/6/25 |
| Paper # | ED99-70 |
| Volume (vol) | vol.99 |
| Number (no) | 146 |
| Page | pp.pp.- |
| #Pages | 7 |
| Date of Issue | |