Presentation | 1994/10/11 GaAs Power FET with Cr-diffusion Setback Layer under the Gate Hidetoshi Furukawa, Kazuki Tateoka, Kazuo Miyatsuji, Akihisa Sugimura, Daisuke Ueda, |
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Abstract(in Japanese) | (See Japanese page) |
Abstract(in English) | A low distortion GaAs power MESFET has been developed by employing semi-insulating setback layer under the gate.The setback region was obtained by diffusing chromium from the Cr, Pt/Au gate metal in self-aligned manner.The novel power FET with the setback layer was found to be insensitive to the surface trapping effects. They showed only 5-6 percentage's frequency dispersion of drain current at 1 GHz comparing with that under DC condition.Then the typical measurement device with the gate width of 36mm exhibited 1. 5dB larger output power at 1 dB gain compression point than that of the conventional one.Moreover,in the π/4 shift-QPSK modulation which has been most popular in digital mobile communication system, the FET exhibited 11 dB smaller adjacent channel leakage power than the conventional one at the output power of 31.5dBm. |
Keyword(in Japanese) | (See Japanese page) |
Keyword(in English) | power FET / Cr-diffusion / Digital mobil communication / π/ sh ift QPSK modulation / Frequency dispersion / Surface trapping effect |
Paper # | ED94-73 |
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Conference Information | |
Committee | ED |
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Conference Date | 1994/10/11(1days) |
Place (in Japanese) | (See Japanese page) |
Place (in English) | |
Topics (in Japanese) | (See Japanese page) |
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Paper Information | |
Registration To | Electron Devices (ED) |
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Language | JPN |
Title (in Japanese) | (See Japanese page) |
Sub Title (in Japanese) | (See Japanese page) |
Title (in English) | GaAs Power FET with Cr-diffusion Setback Layer under the Gate |
Sub Title (in English) | |
Keyword(1) | power FET |
Keyword(2) | Cr-diffusion |
Keyword(3) | Digital mobil communication |
Keyword(4) | π/ sh ift QPSK modulation |
Keyword(5) | Frequency dispersion |
Keyword(6) | Surface trapping effect |
1st Author's Name | Hidetoshi Furukawa |
1st Author's Affiliation | Electrics Research Laboratory,Matsushita Electronics Corporation() |
2nd Author's Name | Kazuki Tateoka |
2nd Author's Affiliation | Electrics Research Laboratory,Matsushita Electronics Corporation |
3rd Author's Name | Kazuo Miyatsuji |
3rd Author's Affiliation | Electrics Research Laboratory,Matsushita Electronics Corporation |
4th Author's Name | Akihisa Sugimura |
4th Author's Affiliation | Electrics Research Laboratory,Matsushita Electronics Corporation |
5th Author's Name | Daisuke Ueda |
5th Author's Affiliation | Electrics Research Laboratory,Matsushita Electronics Corporation |
Date | 1994/10/11 |
Paper # | ED94-73 |
Volume (vol) | vol.94 |
Number (no) | 268 |
Page | pp.pp.- |
#Pages | 6 |
Date of Issue |