Presentation 1994/10/11
A WSi/W self-aligned gate FET for high power amplifier with low voltage supply
Nobuyuki Kasai, Kazuhiko Ito, Shinichi Miyakuni, Kosei Maemura, Kazuya Yamamoto, Hirozo Takano,
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Abstract(in Japanese) (See Japanese page)
Abstract(in English) A WSi, W SAGFET for high power amplifier with low voltage supply has been developed.This novel FET has sufficient high breakdown voltage due to the offset gate structure and n' layer separation from gate edge.Also gate resistance has been reduced using WSi/W double layer structure.As a result,output power of 24.7dBm,power- added efficiency of 54% and adjacent channel leakage power of less than -55dBc have been achieved under drain bias of 3.3V at 1.9GHz.
Keyword(in Japanese) (See Japanese page)
Keyword(in English) Low voltage supply / WSi/ / Offset gate / Separated n'layer / high power FET
Paper # ED94-72
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Conference Information
Committee ED
Conference Date 1994/10/11(1days)
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Paper Information
Registration To Electron Devices (ED)
Language JPN
Title (in Japanese) (See Japanese page)
Sub Title (in Japanese) (See Japanese page)
Title (in English) A WSi/W self-aligned gate FET for high power amplifier with low voltage supply
Sub Title (in English)
Keyword(1) Low voltage supply
Keyword(2) WSi/
Keyword(3) Offset gate
Keyword(4) Separated n'layer
Keyword(5) high power FET
1st Author's Name Nobuyuki Kasai
1st Author's Affiliation Mitsubishi electric corporation()
2nd Author's Name Kazuhiko Ito
2nd Author's Affiliation Mitsubishi electric corporation
3rd Author's Name Shinichi Miyakuni
3rd Author's Affiliation Mitsubishi electric corporation
4th Author's Name Kosei Maemura
4th Author's Affiliation Mitsubishi electric corporation
5th Author's Name Kazuya Yamamoto
5th Author's Affiliation Mitsubishi electric corporation
6th Author's Name Hirozo Takano
6th Author's Affiliation Mitsubishi electric corporation
Date 1994/10/11
Paper # ED94-72
Volume (vol) vol.94
Number (no) 268
Page pp.pp.-
#Pages 6
Date of Issue