| Presentation | 1994/10/11 0.1-μm Au/WSiN Gate GaAs MESFET's Having new BP-LDD structure Kazumi Nishimura, Masami Tokumitsu, Makoto Hirano, Shinji Aoyama, Yasuro Yamane, Kimiyoshi Yamasaki, |
|---|---|
| PDF Download Page | PDF download Page Link |
| Abstract(in Japanese) | (See Japanese page) |
| Abstract(in English) | A new Au, WSiN self-aligned gate GaAs MESFET structure having 0. 1-μm gate length has been developed.In order to suppress the short channel effects,this device has twostep buried players,not only for the n and n'layers but also for the n^+-layer(BP2).Using sidewall Au electroplating technology,the gate resistance has been successfully reduced.The maximum transconductance of 720 mS/mm,the maximum f_T of 105 GHz and the maximum fmax of 233 GHz have been demonstrated. |
| Keyword(in Japanese) | (See Japanese page) |
| Keyword(in English) | WSiN / GaAs / BP-LDD structure / MESFET / Sidewall electroplating technology |
| Paper # | ED94-71 |
| Date of Issue |
| Conference Information | |
| Committee | ED |
|---|---|
| Conference Date | 1994/10/11(1days) |
| Place (in Japanese) | (See Japanese page) |
| Place (in English) | |
| Topics (in Japanese) | (See Japanese page) |
| Topics (in English) | |
| Chair | |
| Vice Chair | |
| Secretary | |
| Assistant | |
| Paper Information | |
| Registration To | Electron Devices (ED) |
|---|---|
| Language | JPN |
| Title (in Japanese) | (See Japanese page) |
| Sub Title (in Japanese) | (See Japanese page) |
| Title (in English) | 0.1-μm Au/WSiN Gate GaAs MESFET's Having new BP-LDD structure |
| Sub Title (in English) | |
| Keyword(1) | WSiN |
| Keyword(2) | GaAs |
| Keyword(3) | BP-LDD structure |
| Keyword(4) | MESFET |
| Keyword(5) | Sidewall electroplating technology |
| 1st Author's Name | Kazumi Nishimura |
| 1st Author's Affiliation | LSI Laboratories,NTT() |
| 2nd Author's Name | Masami Tokumitsu |
| 2nd Author's Affiliation | LSI Laboratories,NTT |
| 3rd Author's Name | Makoto Hirano |
| 3rd Author's Affiliation | LSI Laboratories,NTT |
| 4th Author's Name | Shinji Aoyama |
| 4th Author's Affiliation | LSI Laboratories,NTT |
| 5th Author's Name | Yasuro Yamane |
| 5th Author's Affiliation | LSI Laboratories,NTT |
| 6th Author's Name | Kimiyoshi Yamasaki |
| 6th Author's Affiliation | LSI Laboratories,NTT |
| Date | 1994/10/11 |
| Paper # | ED94-71 |
| Volume (vol) | vol.94 |
| Number (no) | 268 |
| Page | pp.pp.- |
| #Pages | 6 |
| Date of Issue | |