| Presentation | 1993/6/25 Improvements of Fault Detection Efficiency for Failure Analysis of VLSI Memories Using Emission Microscope Connected with VLSI Test System Tatsuya Ishii, Kensaku Naitoh, Kazutoshi Miyamoto, |
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| PDF Download Page | PDF download Page Link |
| Abstract(in Japanese) | (See Japanese page) |
| Abstract(in English) | The increasing density and complexity of VLSI memories such as DRAMs,which become difficult fault locating on the chip.A technique is described for an application of photo emission microscopy to analysis of functional failures in VLSI menories using emission microscope connected with VLSI test system(ATE).The conventional photo emission microscopy technique was used static condition on the chip.This new technique due to dynamically fault isolate leakage and snapping sites,which could greatly improve fault detection efficiency as compared with conventional technique. And we applied this technique to backside photo emission inspection of silicon chip,so function failure sites under the malti-level metal layer and inner lead of LOC(Lead On Chip)on the chip can be analysed. |
| Keyword(in Japanese) | (See Japanese page) |
| Keyword(in English) | Failure Analysis / Emission Microscope / VLSI Test System / VLSI Memories / DRAM |
| Paper # | ED93-48,ICD93-47 |
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| Conference Information | |
| Committee | ED |
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| Conference Date | 1993/6/25(1days) |
| Place (in Japanese) | (See Japanese page) |
| Place (in English) | |
| Topics (in Japanese) | (See Japanese page) |
| Topics (in English) | |
| Chair | |
| Vice Chair | |
| Secretary | |
| Assistant | |
| Paper Information | |
| Registration To | Electron Devices (ED) |
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| Language | JPN |
| Title (in Japanese) | (See Japanese page) |
| Sub Title (in Japanese) | (See Japanese page) |
| Title (in English) | Improvements of Fault Detection Efficiency for Failure Analysis of VLSI Memories Using Emission Microscope Connected with VLSI Test System |
| Sub Title (in English) | |
| Keyword(1) | Failure Analysis |
| Keyword(2) | Emission Microscope |
| Keyword(3) | VLSI Test System |
| Keyword(4) | VLSI Memories |
| Keyword(5) | DRAM |
| 1st Author's Name | Tatsuya Ishii |
| 1st Author's Affiliation | Kita-Itami Works,Mitsubishi Electric() |
| 2nd Author's Name | Kensaku Naitoh |
| 2nd Author's Affiliation | Tada Electric |
| 3rd Author's Name | Kazutoshi Miyamoto |
| 3rd Author's Affiliation | Kita-Itami Works,Mitsubishi Electric |
| Date | 1993/6/25 |
| Paper # | ED93-48,ICD93-47 |
| Volume (vol) | vol.93 |
| Number (no) | 112 |
| Page | pp.pp.- |
| #Pages | 7 |
| Date of Issue | |