| Presentation | 1993/9/16 A Three-Dimensional Interconcect Simulator with a Robast Delauney Terrahedral Partitioning Algorithm Yutaka Akiyama, Susumu Asada, Shigetaka Kumashiro, Norio Tanabe, |
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| PDF Download Page | PDF download Page Link |
| Abstract(in Japanese) | (See Japanese page) |
| Abstract(in English) | An accurate three-dimensional(3D)LCR simulator which can handle any arbitrary interconnect structure has been developed.Failure of Delaunay tetrahedral partitioning due to numerical errors is avoided by using the element topological information.To represent the 3D shape correctly,tetrahedral elements which intersect the solid interface and whose circumsphere centers are out of their own material regions are removed.Exact Delaunay tetrahedral discretization is obtained in 3D shape with the CPU cost proportional to O(n^1.5>)where n is the node number.The calculated capacitance is accurate to less than 2 percent when n is 20000 in a test structure for DRAM cell, bit lines,and the total CPU time is about 18 min on a RISC R4000(50 MHz)based EWS4800/350. |
| Keyword(in Japanese) | (See Japanese page) |
| Keyword(in English) | 3D arbitrary structure / 3D interconect simulator / Control volume method / Tefrahedral partitioning / Delaunay partitioning / Numerical errors |
| Paper # | ED93-80,SDM93-94,VLD93-35 |
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| Conference Information | |
| Committee | ED |
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| Conference Date | 1993/9/16(1days) |
| Place (in Japanese) | (See Japanese page) |
| Place (in English) | |
| Topics (in Japanese) | (See Japanese page) |
| Topics (in English) | |
| Chair | |
| Vice Chair | |
| Secretary | |
| Assistant | |
| Paper Information | |
| Registration To | Electron Devices (ED) |
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| Language | JPN |
| Title (in Japanese) | (See Japanese page) |
| Sub Title (in Japanese) | (See Japanese page) |
| Title (in English) | A Three-Dimensional Interconcect Simulator with a Robast Delauney Terrahedral Partitioning Algorithm |
| Sub Title (in English) | |
| Keyword(1) | 3D arbitrary structure |
| Keyword(2) | 3D interconect simulator |
| Keyword(3) | Control volume method |
| Keyword(4) | Tefrahedral partitioning |
| Keyword(5) | Delaunay partitioning |
| Keyword(6) | Numerical errors |
| 1st Author's Name | Yutaka Akiyama |
| 1st Author's Affiliation | ULSI Device Development Laboratories,NEC Corporation.() |
| 2nd Author's Name | Susumu Asada |
| 2nd Author's Affiliation | ULSI Device Development Laboratories,NEC Corporation. |
| 3rd Author's Name | Shigetaka Kumashiro |
| 3rd Author's Affiliation | ULSI Device Development Laboratories,NEC Corporation. |
| 4th Author's Name | Norio Tanabe |
| 4th Author's Affiliation | ULSI Device Development Laboratories,NEC Corporation. |
| Date | 1993/9/16 |
| Paper # | ED93-80,SDM93-94,VLD93-35 |
| Volume (vol) | vol.93 |
| Number (no) | 216 |
| Page | pp.pp.- |
| #Pages | 8 |
| Date of Issue | |