| Presentation | 1995/10/19 High gate-drain breakdown voltage GaAs MESFETs with undoped GaAs layer on ion-implanted channel layer Hiromasa Fujimoto, Katsuhiko Kawashima, Hiroyuki Masato, Akiyoshi Tamura, |
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| PDF Download Page | PDF download Page Link |
| Abstract(in Japanese) | (See Japanese page) |
| Abstract(in English) | We have developed a new approach to power GaAs MESFETs with planar gate structures, based on the growth technique of an undoped surface GaAs layer on an ion-implanted channel layer. We study the interface between the GaAs substrate and the GaAs layer formed by MBE and MOCVD. It was found that hole trap levels exist in the MBE regrowth interface, but no trap levels exist in the MOCVD regrowth interface by using DLTS analysis. From SIMS analysis, carbon impurities of the MOCVD growth interface are much lower than those of the MBE growth interface. MOCVD growth can achieve the good growth interface characteristics. This undoped GaAs layer increases the gate-drain breakdown voltage and serves as both an ideal passivation layer and an ideal annealing cap of ion implanted channels. This new simple structure offered the high performance power GaAs MESFETs. |
| Keyword(in Japanese) | (See Japanese page) |
| Keyword(in English) | powerGaAs MESFET / MBE / MOCVD / DLTS / SIMS / high breakdown voltage |
| Paper # | ED95-101 |
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| Conference Information | |
| Committee | ED |
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| Conference Date | 1995/10/19(1days) |
| Place (in Japanese) | (See Japanese page) |
| Place (in English) | |
| Topics (in Japanese) | (See Japanese page) |
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| Paper Information | |
| Registration To | Electron Devices (ED) |
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| Language | JPN |
| Title (in Japanese) | (See Japanese page) |
| Sub Title (in Japanese) | (See Japanese page) |
| Title (in English) | High gate-drain breakdown voltage GaAs MESFETs with undoped GaAs layer on ion-implanted channel layer |
| Sub Title (in English) | |
| Keyword(1) | powerGaAs MESFET |
| Keyword(2) | MBE |
| Keyword(3) | MOCVD |
| Keyword(4) | DLTS |
| Keyword(5) | SIMS |
| Keyword(6) | high breakdown voltage |
| 1st Author's Name | Hiromasa Fujimoto |
| 1st Author's Affiliation | Electronics Research Laboratory, Matsushita Electronics Corporation() |
| 2nd Author's Name | Katsuhiko Kawashima |
| 2nd Author's Affiliation | Electronics Research Laboratory, Matsushita Electronics Corporation |
| 3rd Author's Name | Hiroyuki Masato |
| 3rd Author's Affiliation | Electronics Research Laboratory, Matsushita Electronics Corporation |
| 4th Author's Name | Akiyoshi Tamura |
| 4th Author's Affiliation | Electronics Research Laboratory, Matsushita Electronics Corporation |
| Date | 1995/10/19 |
| Paper # | ED95-101 |
| Volume (vol) | vol.95 |
| Number (no) | 314 |
| Page | pp.pp.- |
| #Pages | 8 |
| Date of Issue | |