| Presentation | 1996/1/18 Numerical Analysis of Drain Lag Phenomena in HJFETs on Hole-Trap Substrates Masanobu Nogome, Kazuaki Kunihiro, Yasuo Ohno, |
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| PDF Download Page | PDF download Page Link |
| Abstract(in Japanese) | (See Japanese page) |
| Abstract(in English) | The rate-limiting processes in drain lag phenomena in HJFETs on hole-trap are investigated using numerical device simulation with SRH statistics for deep traps. The drain current slow responses for floating substrates are determined by electron capture or emission, since hole cannot contribute to the trap charge variation there. In addition, the time constants are much smaller than those estimated from the trap parameters due to the charge variation enhancement by internal hole movements. On the other hand, the time constants are determined by hole current travelling from the electrode to the traps in FET with substrate electrodes. Those results indicates that care should be taken which factor determines the drain lags in FETs. |
| Keyword(in Japanese) | (See Japanese page) |
| Keyword(in English) | HJFET / hole-trap / drain lag / deep level / SRH statistics |
| Paper # | ED95-153,MW95-138,ICD95-209 |
| Date of Issue |
| Conference Information | |
| Committee | ED |
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| Conference Date | 1996/1/18(1days) |
| Place (in Japanese) | (See Japanese page) |
| Place (in English) | |
| Topics (in Japanese) | (See Japanese page) |
| Topics (in English) | |
| Chair | |
| Vice Chair | |
| Secretary | |
| Assistant | |
| Paper Information | |
| Registration To | Electron Devices (ED) |
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| Language | JPN |
| Title (in Japanese) | (See Japanese page) |
| Sub Title (in Japanese) | (See Japanese page) |
| Title (in English) | Numerical Analysis of Drain Lag Phenomena in HJFETs on Hole-Trap Substrates |
| Sub Title (in English) | |
| Keyword(1) | HJFET |
| Keyword(2) | hole-trap |
| Keyword(3) | drain lag |
| Keyword(4) | deep level |
| Keyword(5) | SRH statistics |
| 1st Author's Name | Masanobu Nogome |
| 1st Author's Affiliation | Microelectronics Research Laboratories NEC Corporation() |
| 2nd Author's Name | Kazuaki Kunihiro |
| 2nd Author's Affiliation | Microelectronics Research Laboratories NEC Corporation |
| 3rd Author's Name | Yasuo Ohno |
| 3rd Author's Affiliation | Microelectronics Research Laboratories NEC Corporation |
| Date | 1996/1/18 |
| Paper # | ED95-153,MW95-138,ICD95-209 |
| Volume (vol) | vol.95 |
| Number (no) | 449 |
| Page | pp.pp.- |
| #Pages | 6 |
| Date of Issue | |