| Presentation | 1996/1/17 1.5V-Operation GaAs Spike-gate Power FET with 70% Power-added Efficiency Tsuyoshi Tanaka, Hidetoshi Furukawa, Hiroshi Takenaka, Tetsuzo Ueda, Atsushi Noma, Takeshi Fukui, Kazuki Tateoka, Daisuke Ueda, |
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| PDF Download Page | PDF download Page Link |
| Abstract(in Japanese) | (See Japanese page) |
| Abstract(in English) | A GaAs power FET with a spike-gate has been developed for the high efficiency operation under the extremely low voltage supply of 1.5 V. The spike-gate provides both the low on-resistance of 2.2Ω・mm and the high transconductance of 180 ms/mm without reducing the output impedance nor increasing the gate resistance. The implemented device achieved the output power of 31.5 dBm with 65% power-added efficiency at the frequency of 900 MHz.Sub-quarter micron footprints of the spike-gate were defined by using the phase shift lithography. |
| Keyword(in Japanese) | (See Japanese page) |
| Keyword(in English) | Cellular Phone / Spike-gate Power FET / Power-added Efficiency / Phase shift Lithography |
| Paper # | ED95-145,MW95-130,ICD95-201 |
| Date of Issue |
| Conference Information | |
| Committee | ED |
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| Conference Date | 1996/1/17(1days) |
| Place (in Japanese) | (See Japanese page) |
| Place (in English) | |
| Topics (in Japanese) | (See Japanese page) |
| Topics (in English) | |
| Chair | |
| Vice Chair | |
| Secretary | |
| Assistant | |
| Paper Information | |
| Registration To | Electron Devices (ED) |
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| Language | JPN |
| Title (in Japanese) | (See Japanese page) |
| Sub Title (in Japanese) | (See Japanese page) |
| Title (in English) | 1.5V-Operation GaAs Spike-gate Power FET with 70% Power-added Efficiency |
| Sub Title (in English) | |
| Keyword(1) | Cellular Phone |
| Keyword(2) | Spike-gate Power FET |
| Keyword(3) | Power-added Efficiency |
| Keyword(4) | Phase shift Lithography |
| 1st Author's Name | Tsuyoshi Tanaka |
| 1st Author's Affiliation | Electronics Research Laboratory, Matsushita Electronics Corporation() |
| 2nd Author's Name | Hidetoshi Furukawa |
| 2nd Author's Affiliation | Electronics Research Laboratory, Matsushita Electronics Corporation |
| 3rd Author's Name | Hiroshi Takenaka |
| 3rd Author's Affiliation | Electronics Research Laboratory, Matsushita Electronics Corporation |
| 4th Author's Name | Tetsuzo Ueda |
| 4th Author's Affiliation | Electronics Research Laboratory, Matsushita Electronics Corporation |
| 5th Author's Name | Atsushi Noma |
| 5th Author's Affiliation | Electronics Research Laboratory, Matsushita Electronics Corporation |
| 6th Author's Name | Takeshi Fukui |
| 6th Author's Affiliation | Electronics Research Laboratory, Matsushita Electronics Corporation |
| 7th Author's Name | Kazuki Tateoka |
| 7th Author's Affiliation | Electronics Research Laboratory, Matsushita Electronics Corporation |
| 8th Author's Name | Daisuke Ueda |
| 8th Author's Affiliation | Electronics Research Laboratory, Matsushita Electronics Corporation |
| Date | 1996/1/17 |
| Paper # | ED95-145,MW95-130,ICD95-201 |
| Volume (vol) | vol.95 |
| Number (no) | 448 |
| Page | pp.pp.- |
| #Pages | 6 |
| Date of Issue | |