Presentation | 1995/6/22 2V-Gbit/s Low-power Si Bipolar Logic : Current Mirror Control Logic (CMCL) Keiji Kishine, Haruhiko Ichino, Yoshiji Kobayashi, |
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Abstract(in Japanese) | (See Japanese page) |
Abstract(in English) | This paper describes a Low-power Si bipolar circuit for Gbit/s LSIs. To reduce the supply voltage, the current source transistor of ECL circuits are removed and the lower differential pairs of the circuits are replaced by current mirror circuits (Current Mirror Control Logic (CMCL)). This scheme made the 2.0V-high speed operation possible with small currents. This CMCL circuit achieves 3.1-GBit/s(D-F/F) and 4.3GHz(T-F/F)operation with a power supply voltage of -2.0V and power dissipation of 1.8mW/(F/F). |
Keyword(in Japanese) | (See Japanese page) |
Keyword(in English) | bipolar / current mirror / high speed / low power / low voltage / low energy |
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Committee | ED |
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Conference Date | 1995/6/22(1days) |
Place (in Japanese) | (See Japanese page) |
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Topics (in Japanese) | (See Japanese page) |
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Paper Information | |
Registration To | Electron Devices (ED) |
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Language | JPN |
Title (in Japanese) | (See Japanese page) |
Sub Title (in Japanese) | (See Japanese page) |
Title (in English) | 2V-Gbit/s Low-power Si Bipolar Logic : Current Mirror Control Logic (CMCL) |
Sub Title (in English) | |
Keyword(1) | bipolar |
Keyword(2) | current mirror |
Keyword(3) | high speed |
Keyword(4) | low power |
Keyword(5) | low voltage |
Keyword(6) | low energy |
1st Author's Name | Keiji Kishine |
1st Author's Affiliation | NTT LSI Laboratories() |
2nd Author's Name | Haruhiko Ichino |
2nd Author's Affiliation | NTT LSI Laboratories |
3rd Author's Name | Yoshiji Kobayashi |
3rd Author's Affiliation | NTT Electronics Technology |
Date | 1995/6/22 |
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Volume (vol) | vol.95 |
Number (no) | 116 |
Page | pp.pp.- |
#Pages | 7 |
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