Presentation 1997/1/23
A 0.1μm Self-Aligned-Gate GaAs MESFET with Multilayer Interconnection Structure for Ultra-High-Speed ICs
Masami Tokumitsu, Makoto Hirano, Taiichi Otsuji, Satoshi Yamaguchi, Kimiyoshi Yamasaki,
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Abstract(in Japanese) (See Japanese page)
Abstract(in English) We have developed the technologies to fabricate about 0.1-μm-gate-length GaAs MESFETs with a multilayer interconnection structure. We fabricated excellent high-frequency performance of a 0.06-μm-gate-length MESFET having current-gain cutoff frequency (fT) of 168GHz. Using 0.13μm-gate-length MESFETs, we also fabricated an ultra-high-speed decision circuit operating up to 32Gbit/s.
Keyword(in Japanese) (See Japanese page)
Keyword(in English) WSiN / GaAs / MESFET / fT / Multilayer interconnection / Decision circuit
Paper # ED96-192,MW96-155,ICD96-180
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Committee ED
Conference Date 1997/1/23(1days)
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Registration To Electron Devices (ED)
Language JPN
Title (in Japanese) (See Japanese page)
Sub Title (in Japanese) (See Japanese page)
Title (in English) A 0.1μm Self-Aligned-Gate GaAs MESFET with Multilayer Interconnection Structure for Ultra-High-Speed ICs
Sub Title (in English)
Keyword(1) WSiN
Keyword(2) GaAs
Keyword(3) MESFET
Keyword(4) fT
Keyword(5) Multilayer interconnection
Keyword(6) Decision circuit
1st Author's Name Masami Tokumitsu
1st Author's Affiliation NTT System Electronics Laboratories()
2nd Author's Name Makoto Hirano
2nd Author's Affiliation NTT System Electronics Laboratories
3rd Author's Name Taiichi Otsuji
3rd Author's Affiliation NTT System Electronics Laboratories
4th Author's Name Satoshi Yamaguchi
4th Author's Affiliation NTT System Electronics Laboratories
5th Author's Name Kimiyoshi Yamasaki
5th Author's Affiliation NTT System Electronics Laboratories
Date 1997/1/23
Paper # ED96-192,MW96-155,ICD96-180
Volume (vol) vol.96
Number (no) 461
Page pp.pp.-
#Pages 6
Date of Issue