Presentation | 2001/12/14 Quasi-Worst-Condition Built-In-Self-Test Scheme for a 4-Mb Loadless CMOS Four-Transistor SRAM Macro Koichi Takeda, Yoshiharu Aimoto, Kazuyuki Nakamura, Sadaaki Masuoka, Katsuyuki Ishikawa, Kenji Noda, Toshio Takeshima, Tatsunori Murotani, |
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PDF Download Page | PDF download Page Link |
Abstract(in Japanese) | (See Japanese page) |
Abstract(in English) | We have developed a 4-Mb loadless CMOS four-transistor SRAM macro that has two 16-Kb redundancy blocks per 1-Mb block using a 0.18μm CMOS logic process technology. To reduce cost in our SRAM macro, we have eliminated the fuse and employ instead a Built In Self Test at the time of the system start-up. We have developed a quasi-worst-condition BIST scheme that employs word-line voltage level adjustment. |
Keyword(in Japanese) | (See Japanese page) |
Keyword(in English) | loadless-4-transistor SRAM / static noise margin / worst-condition / test / BIST / BISR |
Paper # | CPM-127,ICD-179 |
Date of Issue |
Conference Information | |
Committee | CPM |
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Conference Date | 2001/12/14(1days) |
Place (in Japanese) | (See Japanese page) |
Place (in English) | |
Topics (in Japanese) | (See Japanese page) |
Topics (in English) | |
Chair | |
Vice Chair | |
Secretary | |
Assistant |
Paper Information | |
Registration To | Component Parts and Materials (CPM) |
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Language | JPN |
Title (in Japanese) | (See Japanese page) |
Sub Title (in Japanese) | (See Japanese page) |
Title (in English) | Quasi-Worst-Condition Built-In-Self-Test Scheme for a 4-Mb Loadless CMOS Four-Transistor SRAM Macro |
Sub Title (in English) | |
Keyword(1) | loadless-4-transistor SRAM |
Keyword(2) | static noise margin |
Keyword(3) | worst-condition |
Keyword(4) | test |
Keyword(5) | BIST |
Keyword(6) | BISR |
1st Author's Name | Koichi Takeda |
1st Author's Affiliation | NEC Corporation() |
2nd Author's Name | Yoshiharu Aimoto |
2nd Author's Affiliation | NEC Corporation |
3rd Author's Name | Kazuyuki Nakamura |
3rd Author's Affiliation | NEC Corporation |
4th Author's Name | Sadaaki Masuoka |
4th Author's Affiliation | NEC Corporation |
5th Author's Name | Katsuyuki Ishikawa |
5th Author's Affiliation | NEC Corporation |
6th Author's Name | Kenji Noda |
6th Author's Affiliation | NEC Corporation |
7th Author's Name | Toshio Takeshima |
7th Author's Affiliation | NEC Corporation |
8th Author's Name | Tatsunori Murotani |
8th Author's Affiliation | NEC Corporation |
Date | 2001/12/14 |
Paper # | CPM-127,ICD-179 |
Volume (vol) | vol.101 |
Number (no) | 517 |
Page | pp.pp.- |
#Pages | 6 |
Date of Issue |